Invention Application
- Patent Title: SEMICONDUCTOR DEVICE LAYOUT AND METHOD FOR FORMING SAME
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Application No.: PCT/US2018/032546Application Date: 2018-05-14
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Publication No.: WO2018213178A1Publication Date: 2018-11-22
- Inventor: LOSEE, Peter Almern , BOLOTNIKOV, Alexander , KENNERLY, Stacey Joy , KRETCHMER, James William
- Applicant: GENERAL ELECTRIC COMPANY
- Applicant Address: 1 River Road Schenectady, NY 12345 US
- Assignee: GENERAL ELECTRIC COMPANY
- Current Assignee: GENERAL ELECTRIC COMPANY
- Current Assignee Address: 1 River Road Schenectady, NY 12345 US
- Agency: DIMAURO, Peter T. et al.
- Priority: US15/596,977 20170516
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L21/04 ; H01L21/768 ; H01L29/423 ; H01L29/739
Abstract:
A semiconductor device is provided. The semiconductor device includes a semiconductor device layer having silicon carbide and having an upper surface and a lower surface. The semiconductor device also includes a heavily doped body region formed in the upper surface of the semiconductor device layer. The semiconductor device further includes a gate stack formed adjacent to and on top of the upper surface of the semiconductor device layer, wherein the gate stack is not formed adjacent to the heavily doped body region.
Information query
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