A memory structure includes a conductive interconnect disposed above a substrate, a memory device disposed above the conductive interconnect and coupled with the conductive interconnect. The memory device has sidewalls and an uppermost surface. For memory device and fabrication enablement, a top hat electrode is disposed on the memory device. The top hat electrode has sidewalls, a lowermost surface and an uppermost surface. The sidewalls of the top hat electrode extend beyond the sidewalls of the memory device. The top hat electrode has a lowermost surface area that is larger than an area of the uppermost surface of the memory device. A second conductive interconnect is disposed on the top hat electrode. The second conductive interconnect includes a via having sidewalls and a lowermost surface that is in contact with the uppermost surface of the top hat electrode.