The present invention is provided with a signal synthesis circuit (3) which, upon receipt of a third signal having an opposite-phase component to that of a signal obtained by synthesizing a signal the amplitude of which has been changed by a first variable-amplitude component (1) and a signal the amplitude of which has been changed by a second variable-amplitude component (2), synthesizes the signal the amplitude of which has been changed by the first variable-amplitude component (1), the signal the amplitude of which has been changed by the second variable-amplitude component (2), and the third signal.