A circuit (100) including a first processing element (110) having a first output configured to couple to a voltage control circuit (112), a second output configured to couple to a gate terminal of a first transistor (116), and a third output configured to couple to a first node (118) and a control circuit (114). The control circuit (114) includes a second processing element having multiple outputs, a second transistor having a gate terminal configured to couple to one of the outputs of the second processing element, a first terminal configured to couple to a second node (134) and to a drain terminal of the first transistor (116), and a second terminal, and a third transistor having a gate terminal configured to couple to a second of the outputs of the second processing element, a first terminal configured to couple to a third node (132), and a second terminal.