A storage array includes multiple wordlines of storage cells that can be selectively charged to an erase voltage or an inhibit voltage. Control logic associated with the storage array can perform erase verify in stages. On a first erase verify pass, the control logic can set wordlines of an erase block or subblock to a first erase voltage. On a second erase verify pass, the control logic can trigger a second erase verify pulse and set passing wordlines to an inhibit voltage, and failing wordlines to a second erase voltage higher than the first voltage. Inhibiting the already passing wordlines can reduce threshold voltage differences among the wordlines.