A power on reset circuit comprises terminals (101, 102) for reference and supply potentials (VSS, VDD) and a voltage divider (130) coupled therebetween. First and second transistors (110, 120) of a bandgap circuit are resistively coupled to the reference potential terminal (101) and have bases connected to the voltage divider (130). Current mirrors (150, 160, 170) couple the collectors of the first and second transistors (110, 120) to an output terminal (103) providing an output signal (POR) indicating a power on reset condition. A first compensation transistor (180) is coupled between the collector of one of the transistors (120) and the reference potential terminal (101), and a second compensation transistor (190) is coupled between the output terminal (103) and the reference potential terminal (101) to compensate the effect of parasitic substrate currents in response to an external interference.