A hardware accelerator, a data processing method, a system-level chip, and a medium. An instruction set processed by the hardware accelerator comprises: a data flow control instruction used for executing data flow control; a conventional computing instruction used for executing conventional computing so as to complete conventional computing in a recurrent neural network; a special computing instruction used for executing special computing so as to complete special computing in the recurrent neural network; an exponential shift instruction used for executing an exponential shift so as to complete data normalization in recurrent neural network computing; and a data transfer instruction used for executing data transfer so as to complete, during recurrent neural network computing, a data transfer operation between different registers as well as a data transfer operation between registers and memories. By means of the described technical solution, the present application can effectively improve the utilization rate of computing resources of a hardware accelerator used for running a recurrent neural network, and can effectively avoid conflicts in the aspects of data and resources.