This semiconductor package comprises: a first interposer including a first surface and a second surface; a second interposer including a third surface and a fourth surface and disposed alongside the first interposer in a first direction; a third interposer including a fifth surface and a sixth surface and positioned between the first interposer and the second interposer in the first direction; a first semiconductor element overlapping the first surface and the fifth surface in plan view; and a second semiconductor element overlapping the third surface and the fifth surface in plan view. The third interposer includes wiring electrically connecting the first semiconductor element and the second semiconductor element.