Invention Application
- Patent Title: ACTIVATION BUFFER ARCHITECTURE FOR DATA-REUSE IN A NEURAL NETWORK ACCELERATOR
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Application No.: PCT/CN2021/108594Application Date: 2021-07-27
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Publication No.: WO2023004570A1Publication Date: 2023-02-02
- Inventor: WADHWA, Sameer , MOHAN, Suren , ZHU, Peiyu , LI, Ren , SRIVASTAVA, Ankit , MIRHAJ, Seyed Arash
- Applicant: QUALCOMM INCORPORATED , WADHWA, Sameer , MOHAN, Suren , ZHU, Peiyu , LI, Ren , SRIVASTAVA, Ankit , MIRHAJ, Seyed Arash
- Applicant Address: Attn: International IP Administration; 5775 Morehouse Drive; 5775 Morehouse Drive; 5775 Morehouse Drive; 5775 Morehouse Drive; 5775 Morehouse Drive; 5775 Morehouse Drive
- Assignee: QUALCOMM INCORPORATED,WADHWA, Sameer,MOHAN, Suren,ZHU, Peiyu,LI, Ren,SRIVASTAVA, Ankit,MIRHAJ, Seyed Arash
- Current Assignee: QUALCOMM INCORPORATED,WADHWA, Sameer,MOHAN, Suren,ZHU, Peiyu,LI, Ren,SRIVASTAVA, Ankit,MIRHAJ, Seyed Arash
- Current Assignee Address: Attn: International IP Administration; 5775 Morehouse Drive; 5775 Morehouse Drive; 5775 Morehouse Drive; 5775 Morehouse Drive; 5775 Morehouse Drive; 5775 Morehouse Drive
- Agency: NTD PATENT & TRADEMARK AGENCY LTD.
- Main IPC: G06N3/04
- IPC: G06N3/04 ; G06N3/063
Abstract:
Certain aspects provide an apparatus for signal processing in a neural network. The apparatus generally includes computation circuitry configured to perform a convolution operation, the computation circuitry having multiple input rows, and an activation buffer having multiple buffer segments coupled to the multiple input rows of the computation circuitry, respectively. In some aspects, each of the multiple buffer segments comprises a first multiplexer having a plurality of multiplexer inputs, and each of the plurality of multiplexer inputs of one of the first multiplexers on one of the multiple buffer segments is coupled to a data output of the activation buffer on another one of the multiple buffer segments.
Information query