An array substrate is provided. The array substrate includes K number of reset signal lines respectively configured to provide reset signals to reset transistors in K columns pixel driving circuits of the array substrate. The K number of reset signal lines includes a plurality of third reset signal lines in (2k-1) -th columns of K columns, K and k being positive integers, 1 ≤ k ≤ (K/2); and a plurality of fourth reset signal lines in (2k) -th columns of the K columns. A respective third reset signal line and a respective fourth reset signal line have different line patterns.