发明申请
- 专利标题： MACHINE LEARNING-BASED INTEGRATED CIRCUIT PVT TEST CASE SELECTION FOR TIMING ANALYSIS
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申请号： PCT/US2022/075306申请日： 2022-08-23
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公开(公告)号： WO2023049577A1公开(公告)日： 2023-03-30
- 发明人: KOSTAS, Lindsey, Makana , PATTANAYAK, Santanu , JAIN, Tushit
- 申请人： QUALCOMM INCORPORATED
- 申请人地址： Attn: International IP Administration
- 专利权人： QUALCOMM INCORPORATED
- 当前专利权人： QUALCOMM INCORPORATED
- 当前专利权人地址： Attn: International IP Administration
- 代理机构： READ, Randol, W. et al.
- 优先权： US17/484,536 2021-09-24
- 主分类号： G06F30/3312
- IPC分类号： G06F30/3312 ; G06F30/27 ; G06F119/18 ; G06F119/22 ; G06F119/12
摘要：
Testing integrated circuit designs based on test cases selected using machine learning models by receiving a plurality of test cases for an integrated circuit. An embedding data set is generated from the plurality of test cases (730). A respective embedding for a respective test case of the plurality of test cases includes a mapping of the respective test case into a multidimensional space. A plurality of test case clusters is generated based on a clustering model and the embedding data set. A plurality of critical test cases for testing the integrated circuit is selected based on the plurality of test case clusters. The integrated circuit is timed based on the plurality of critical test cases and a hard macro defining the integrated circuit.
