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公开(公告)号：EP0284060A3
公开(公告)日：1989-07-19
申请号：EP88104730.2
申请日：1988-03-24
发明人： Heslin, Peter M.
IPC分类号： G06F9/26
CPC分类号： G06F9/264
摘要： A microprocessor integrated circuit chip includes a plurality of functional areas containing a large number of widely distributed signal sources. An on-chip selection network is distributed on the chip which enables the selection of signals from the large number of sources under microinstruction control without any decrease in chip performance. The network includes an access bus which is distributed to the functional areas as a function of the concentration of signals provided by the sources. Individual decoders are strategically located on the chip and connect in common to a control bus. Each decoder connects to a plurality of switches for linking the sources of a functional area to the access bus. A selector circuit terminates the access bus at one end. Under microprogram control, the selector circuit is enabled to select which final source signal is applied to the functional area containing branching circuits for selecting a next microinstruction to be executed by the microprocessor.
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公开(公告)号：EP0284060A2
公开(公告)日：1988-09-28
申请号：EP88104730.2
申请日：1988-03-24
发明人： Heslin, Peter M.
IPC分类号： G06F9/26
CPC分类号： G06F9/264
摘要： A microprocessor integrated circuit chip includes a plurality of functional areas containing a large number of widely distributed signal sources. An on-chip selection network is distributed on the chip which enables the selection of signals from the large number of sources under microinstruction control without any decrease in chip performance. The network includes an access bus which is distributed to the functional areas as a function of the concentration of signals provided by the sources. Individual decoders are strategically located on the chip and connect in common to a control bus. Each decoder connects to a plurality of switches for linking the sources of a functional area to the access bus. A selector circuit terminates the access bus at one end. Under microprogram control, the selector circuit is enabled to select which final source signal is applied to the functional area containing branching circuits for selecting a next microinstruction to be executed by the microprocessor.
摘要翻译： 微处理器集成电路芯片包括包含大量广泛分布的信号源的多个功能区域。 片上选择网络分布在芯片上，能够在微指令控制下选择来自大量源的信号，而不会降低芯片性能。 该网络包括作为由源提供的信号的集中的函数而分配到功能区的访问总线。 单个解码器在策略上位于芯片上，并且共同连接到控制总线。 每个解码器连接到多个开关，用于将功能区域的源连接到接入总线。 选择器电路在一端终止接入总线。 在微程序控制下，选择器电路能够选择哪个最终的源信号被施加到包含用于选择由微处理器执行的下一个微指令的分支电路的功能区域。
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公开(公告)号：EP0284060B1
公开(公告)日：1993-07-21
申请号：EP88104730.2
申请日：1988-03-24
发明人： Heslin, Peter M.
IPC分类号： G06F9/26
CPC分类号： G06F9/264
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