Circuit and method of interconnecting content addressable memory
    1.
    发明公开
    Circuit and method of interconnecting content addressable memory 失效
    互连内容寻址存储器的电路和方法

    公开(公告)号:EP0644553A2

    公开(公告)日:1995-03-22

    申请号:EP94114546.8

    申请日:1994-09-15

    申请人: CODEX CORPORATION

    IPC分类号: G11C15/00 G11C15/04

    CPC分类号: G11C15/04

    摘要: A data compressor (14) generates codewords representative of the location and length of a string match between an input data stream and a CAM array vocabulary table (22). A data decompressor (16) looks up the codewords for a string match in its vocabulary table. The CAM array (50,52,54,56) is arranged in a serpentine configuration to reduce track layout. A column priority encoder (74) reverses the priority of alternate rows to maintain the logical flow through the CAM array. The CAM array uses a flipflop (122) with a common control circuit to transfer and refresh data through the flipflop.

    摘要翻译: 数据压缩器(14)产生表示输入数据流和CAM阵列词汇表(22)之间的字符串匹配的位置和长度的码字。 数据解压缩器(16)在其词汇表中查找字符串匹配的码字。 CAM阵列(50,52,54,56)以蛇形结构布置以减少轨道布局。 列优先级编码器(74)反转交替行的优先级以维持通过CAM阵列的逻辑流。 CAM阵列使用具有公共控制电路的触发器(122)来通过触发器来传输和刷新数据。

    Circuit and method of interconnecting content addressable memory
    3.
    发明公开
    Circuit and method of interconnecting content addressable memory 失效
    为内容可寻址存储器的连接的方法和装置。

    公开(公告)号:EP0644553A3

    公开(公告)日:1995-09-06

    申请号:EP94114546.8

    申请日:1994-09-15

    申请人: CODEX CORPORATION

    IPC分类号: G11C15/00 G11C15/04

    CPC分类号: G11C15/04

    摘要: A data compressor (14) generates codewords representative of the location and length of a string match between an input data stream and a CAM array vocabulary table (22). A data decompressor (16) looks up the codewords for a string match in its vocabulary table. The CAM array (50,52,54,56) is arranged in a serpentine configuration to reduce track layout. A column priority encoder (74) reverses the priority of alternate rows to maintain the logical flow through the CAM array. The CAM array uses a flipflop (122) with a common control circuit to transfer and refresh data through the flipflop.