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1.发明授权
公开(公告)号：EP0556209B1
公开(公告)日：1995-10-04
申请号：EP91918488.7
申请日：1991-10-26
发明人： LORECK, Heinz , ENGELMANN, Mario
IPC分类号： H02P3/08
CPC分类号： H02P3/08
摘要： Described is a circuit for limiting the cut-off voltage which occurs when an actuator motor (M) is controlled by means of width-modulated d.c. pulses. The circuit comprises a power transistor (T2) which is turned on by a capacitor (C) for a short time interval when a cut-off voltage occurs, thus limiting the cut-off voltage. The transistor (T2) then reverts to the high-resistance state again. This prevents the actuator motor (M) from shorting during the phase in which the motor is reset by spring action to its O-position.
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公开(公告)号：EP0556191B1
公开(公告)日：1995-08-09
申请号：EP91916333.7
申请日：1991-09-11
CPC分类号： H02H7/0833 , H02H3/445
摘要： Disclosed is a control circuit for a servomotor (M), the circuit using current pulses and supplying a current-controlled final stage (1). The growth in current is monitored, when the final stage (1) is driven, to detect a possible short-circuit in the servomotor (M) with respect to the mains supply (+UB). A particularly high current (IK) after a measurement time (TM) which begins with the turning-on of the final-stage transistor (LT) indicates a short-circuit.
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公开(公告)号：EP0695250B1
公开(公告)日：1997-06-11
申请号：EP94911160.3
申请日：1994-03-12
发明人： ZYDEK, Michael , FEY, Wolfgang , ENGELMANN, Mario
IPC分类号： B60T8/88
CPC分类号： B60T8/885 , B60T17/22 , B60T2270/402 , H03K17/302 , H03K17/6874
摘要： A circuit for triggering warning lamps has an additional circuit (5) containing an automatic transistor circuit (P-FET3, P-FET4, R1) with a triggering circuit connected to the supply voltages (VCC5, VCC12). If the supply voltages are in order, the triggering circuit keeps the transistor blocked. If the power fails (VCC5 and/or VCC12), the transistors (P-FET3, P-FET4) of the automatic transistor circuit (P-FET3, P-FET3, R1) open a current path from the warning lamp terminal (WL-OUT) to the control terminal (G) of the power driver (2), making it possible for the power driver (2) and hence the warning lamp (3) to be switched on.
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公开(公告)号：EP0842073A1
公开(公告)日：1998-05-20
申请号：EP96923879.0
申请日：1996-06-20
发明人： ENGELMANN, Mario , ZYDEK, Michael , ZINKE, Olaf , FEY, Wolfgang
CPC分类号： B60R16/03 , B60T8/885 , B60T8/90 , B60T2270/406 , H03K17/082
摘要： A process is disclosed for monitoring a final stage component (1, 1') to which a plurality of inductive loads (L1, L2, Ln) are connected. The current that flows through these inductive loads is regulated by cyclically driving the end stages (8). The current generated in the locking phases of the end stages by the inductively stored energy is partially or temporarily led through a common current measurement device (RRCS, 4) and evaluated for testing the final stages, including the inductive loads (L1, L2, Ln).
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公开(公告)号：EP0695250A1
公开(公告)日：1996-02-07
申请号：EP94911160.0
申请日：1994-03-12
发明人： ZYDEK, Michael , FEY, Wolfgang , ENGELMANN, Mario
CPC分类号： B60T8/885 , B60T17/22 , B60T2270/402 , H03K17/302 , H03K17/6874
摘要： A circuit for triggering warning lamps has an additional circuit (5) containing an automatic transistor circuit (P-FET3, P-FET4, R1) with a triggering circuit connected to the supply voltages (VCC5, VCC12). If the supply voltages are in order, the triggering circuit keeps the transistor blocked. If the power fails (VCC5 and/or VCC12), the transistors (P-FET3, P-FET4) of the automatic transistor circuit (P-FET3, P-FET3, R1) open a current path from the warning lamp terminal (WL-OUT) to the control terminal (G) of the power driver (2), making it possible for the power driver (2) and hence the warning lamp (3) to be switched on.
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6.发明公开
公开(公告)号：EP0817975A1
公开(公告)日：1998-01-14
申请号：EP96902284.0
申请日：1996-02-21
发明人： ZYDEK, Michael , FEY, Wolfgang , ZINKE, Olaf , ENGELMANN, Mario
CPC分类号： B60T8/885 , B60T2270/406 , G06F11/28
摘要： In order to monitor a data processing circuit containing two (or more) microprocessors (MP1, MP2) on a shared chip and interconnected by data lines (1), said microprocessors generate data in common which form a data word sequence and are transmitted to a monitoring circuit (4) at predetermined times. The monitoring circuit (4) is on a separate chip (IC2). The data words of the data word sequence are monitored by the monitoring circuit according to the content and time of occurrence of the individual data words. It is an advantage to compose the individual data words of partwords generated by different algorithms.
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