公开(公告)号：EP1286469A1

公开(公告)日：2003-02-26

申请号：EP01118427.2

申请日：2001-07-31

申请人： Infineon Technologies AG

发明人： Raychaudhuri, Arindam

IPC分类号： H03K19/00

CPC分类号： H03K19/0005

摘要： The invention relates to an output driver for integrated circuits comprising

at least one driver circuit for driving an external circuit (20), the driver circuit having
at least one data input (DATAIN) connectable to the integrated circuit;
at least one data output (DQ) connectable to a transmission line (18) leading to the external circuit (20) ; and
impedance adjusting means (24) for adjusting the output impedance of the driver circuit according to determinable impedance adjusting data (30-p, 30-n);
at least one dummy circuit (32) comprising a dummy driver circuit (34) and a dummy transmission line (40), the dummy driver circuit (34) and the dummy transmission line (40) being electrical replica of the driver circuit and of the transmission line (18), respectively; and
at least one impedance control circuit (22) for controlling the output impedance of the driver circuit, the impedance control circuit being connected to the dummy circuit (32) and the impedance adjusting means (24);
wherein the impedance control circuit (22) is adapted to control the impedance of the driver circuit by determining the impedance adjusting data (30-p, 30-n) necessary for matching the output impedance of the dummy driver circuit (34) to the characteristic impedance of the dummy transmission line (40) and outputting the determined impedance adjusting data (30-p, 30-n) to the impedance adjusting means (24) of the driver circuit (32).

公开(公告)号：EP1187327A1

公开(公告)日：2002-03-13

申请号：EP00119139.4

申请日：2000-09-04

申请人： Infineon Technologies AG

发明人： Raychaudhuri, Arindam

IPC分类号： H03K3/037

CPC分类号： H03K3/35625 ,  H03K3/0372

摘要： In the present invention, an edge-triggered D-Flip-Flop circuit with a master/slave configuration is disclosed. The master circuit (MA) comprises only one master switch (T1) controlled by a clock signal ( C ¯ ) and followed by a first inverter (I1). The slave circuit (SL) comprises a slave switch (T2) followed by a second inverter (I2) and a regenerative feedback-loop (I3, T3). Master and slave switches (T1, T2) can easily be realised using pass-transistors thus achieving small chip area. The Flip-Flop can easily be amended by set and reset means (T4, T5) and is preferably suitable for mass applications like memory and microprocessor chips.

摘要翻译： 在本发明中，公开了具有主/从配置的边沿触发D触发电路。 主电路（MA）仅包括由时钟信号（C）控制的一个主开关（T1），其后是第一反相器（I1）。 从电路（SL）包括从开关（T2），后跟第二反相器（I2）和再生反馈回路（I3，T3）。 主从开关（T1，T2）可以通过传统晶体管轻松实现，从而实现小芯片面积。 触发器可以通过设置和复位手段（T4，T5）轻松修改，最适合大批量应用，如存储器和微处理器芯片。