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公开(公告)号：EP4415199A3
公开(公告)日：2024-09-11
申请号：EP24154129.1
申请日：2024-01-26
发明人： Ellendula, Shiva Prasad , Ponnusamy, Soundara Mohan , Nagabhushanrao, Pradeep Tolakanahalli , Lipare, Mahendrakumar Haribhau
CPC分类号： H02J3/0012 , H02J9/062 , G01R31/42 , H02H7/1227 , H02M7/539 , H02M1/0032 , H02M1/10 , H02M1/0067 , H02M1/0083 , H02M7/48
摘要： A power conditioner includes an input configured to be coupled to a main-power source and an output configured to receive power from within the power conditioner from the main-power source, a backup-power source, or both. The power conditioner includes an inverter, at least one processor, and a memory storing instructions that, when executed by the processor, cause the processor to perform a method. The method includes receiving an inverter-off signal, receiving an output-voltage level above a threshold output-voltage level, and preventing activation of the inverter in response to at least receiving the inverter-off signal and the output-voltage level above the threshold output-voltage level.
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公开(公告)号：EP4415199A2
公开(公告)日：2024-08-14
申请号：EP24154129.1
申请日：2024-01-26
发明人： Ellendula, Shiva Prasad , Ponnusamy, Soundara Mohan , Nagabhushanrao, Pradeep Tolakanahalli , Lipare, Mahendrakumar Haribhau
CPC分类号： H02J3/0012 , H02J9/062 , G01R31/42
摘要： A power conditioner includes an input configured to be coupled to a main-power source and an output configured to receive power from within the power conditioner from the main-power source, a backup-power source, or both. The power conditioner includes an inverter, at least one processor, and a memory storing instructions that, when executed by the processor, cause the processor to perform a method. The method includes receiving an inverter-off signal, receiving an output-voltage level above a threshold output-voltage level, and preventing activation of the inverter in response to at least receiving the inverter-off signal and the output-voltage level above the threshold output-voltage level.
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