Line support processor for data transfer system
    151.
    发明公开
    Line support processor for data transfer system 失效
    用于数据传输系统的线路支持处理器

    公开(公告)号:EP0105688A3

    公开(公告)日:1985-05-22

    申请号:EP83305724

    申请日:1983-09-26

    IPC分类号: G06F03/04

    CPC分类号: G06F13/385

    摘要: Data transfers between remote data sets, data terminals and a main host computer are controlled by a peripheral-controller designated as a Line Support Processor (LSP). The LSP manages a plurality of line adapters, each of which handles a separate data comm line. The LSP includes internal processor means and interface circuit means to effectuate data transfer operations using a variety of protocols and systems both for bit-oriented and byte-oriented data transfers.

    摘要翻译: 远程数据集,数据终端和主主机之间的数据传输由指定为线路支持处理器(LSP)的外围控制器控制。 LSP管理多个线路适配器,每个线路适配器处理单独的数据通信线路。 LSP包括内部处理器装置和接口电路装置,用于使用各种协议和系统进行数据传输操作,用于面向位和面向字节的数据传输。

    Improvements in and relating to printed-circuit board edge connectors
    153.
    发明公开
    Improvements in and relating to printed-circuit board edge connectors 失效
    印刷电路板边缘连接器的改进和相关

    公开(公告)号:EP0083862A3

    公开(公告)日:1985-05-22

    申请号:EP82306849

    申请日:1982-12-21

    IPC分类号: H01R23/70

    CPC分类号: H01R12/88

    摘要: A system for providing edge connection to printed-circuit boards 40 and the like has very low insertion force and almost no contact wear, so avoiding the disadvantages of conventional edge connection systems, by employing a connector comprising two mutually pivotable arms 10 and 12 or 72 and 74 having protrusions 14 and 16 or 76 and 78 at their distal ends which are separable in response to the board being introduced between the protrusions 14 and 16 or 76 and 78 to separate spring contact sections 32 34 far enough to allow insertion of the board 40 without rubbing thereagainst, the protrusions 14 and 16 or 76 and 78 falling into a void 48 94 at the end of insertion to allow the spring contact sections 32 34 to impinge upon pads 44 96 on the board 40 with the coming back together of the arms 10 and 12 or 72 and 74, the system working in reverse for the withdrawal of a board 40.

    Memory mapping unit
    154.
    发明公开
    Memory mapping unit 失效
    存储映射单元

    公开(公告)号:EP0080823A3

    公开(公告)日:1985-05-22

    申请号:EP82306099

    申请日:1982-11-16

    发明人: Koos, Larry W.

    IPC分类号: G11C09/06

    CPC分类号: G06F12/0661

    摘要: In a system where a plurality of memory boards, which can be of different sizes, are connected to a common address buss and data buss, it is disclosed that a binary adder adds the 2's complement of the contents of base address register with significant bits obtained from the address buss. A series of logic gates are connected to the output of the binary adder and a board size mask register. The logic gates perform a logical AND operation on the binary adder output and the output of board size mask register. The outputs from the logic gates in turn are connected to a multiple input NOR gate. When all the inputs are logical "zero", a board enable command is generated which will activate a memory board transceiver, which will then enable the specified memory board to receive or transmit data over the data buss.

    Data communications network
    155.
    发明公开
    Data communications network 失效
    数据通信网络

    公开(公告)号:EP0073710A3

    公开(公告)日:1985-05-22

    申请号:EP82401554

    申请日:1982-08-19

    IPC分类号: G06F03/04

    CPC分类号: G06F13/385

    摘要: Base connection modules are used to house slide-in cards which form a Network Support Processor which executes data transfer operations for up to four main host computers. One Network Support Processor can control up to four Line Support Processors, each one of which manages up to 16 Line Adapters connected, via data communication lines, to remote terminals. The Line Support Processor, via its Line Adapters, handles a wide variety of communication line disciplines but provides a common discipline to its Network Support Processor and the host computer.

    Interrupt system for peripheral controller
    157.
    发明公开
    Interrupt system for peripheral controller 失效
    外围控制器中断系统

    公开(公告)号:EP0083002A3

    公开(公告)日:1985-05-15

    申请号:EP82111433

    申请日:1982-12-09

    IPC分类号: G06F03/04

    CPC分类号: G06F9/461 G06F13/385

    摘要: An interrupt network whereby, upon completion of a data transfer cycle between a host computer and peripheral-controller or completion of a data transfer cycle between a peripheral terminal and peripheral-controller, the peripheral-controller is placed in an interrupt mode (background mode) and institutes an interrupt service routine. The normal mode data in the peripheral-controller is stored for re-use upon return to normal mode.

    摘要翻译: 一种中断网络,在完成主计算机和外围控制器之间的数据传输周期或完成外围终端和外围控制器之间的数据传输周期之后,外围控制器被置于中断模式(背景模式) 并制定中断服务程序。 存储外围控制器中的正常模式数据,以便在返回正常模式时重新使用。