FET cell usable in storage or switching devices
    21.
    发明公开
    FET cell usable in storage or switching devices 失效
    对存储器或开关装置FET单元。

    公开(公告)号:EP0040701A1

    公开(公告)日:1981-12-02

    申请号:EP81103165.7

    申请日:1981-04-28

    IPC分类号: G11C11/34 G11C17/00 H01L29/60

    CPC分类号: G11C16/0416 H01L29/7882

    摘要: An improved memory system is provided for charging and discharging a conductive plate such as a floating gate (22) of a field effect transistor (10) with a charge injector (28) controlled by a low single polarity voltage pulse. In the system of the invention, the conductive plate may be a floating gate (22) of a field effect transistor (10) which also includes first (26) and second (30) or dual control gates. A single or double graded band gap layer, such as a silicon rich layer of silicon dioxide is disposed only between the floating gate (22) and the first control gate (26) forming a capacitor (24) having a given capacitance with a larger capacitor disposed between the second (30) control gate and the floating gate (22). These cells or transistors may be used in an array for storing for long periods of time, on the order of 10 years or more, binary digits of information representing a 0 od a 1 depending upon whether a charge is stored on the floating gate. When using these cells in a memory array, information may be written into or erased from each of the cells individually or a blanket erase may be employed for the entire or a selected section of the array. To write and to erase a cell, a low single polarity voltage is employed. Several embodiments of the invention are disclosed including one embodiment wherein the dual gates are located on one side of the floating gate, a second embodiment which uses a diffusion in a semiconductor substrate as one of the control gates and a third embodiment wherein one of the control gates is disposed on one side of, or above, the floating gate and the other control gate is disposed on the other side of, or below, the floating gate near the surface of the channel region of the transistor.

    Isolierschicht-Feldeffektransistor
    22.
    发明公开
    Isolierschicht-Feldeffektransistor 失效
    Isolierschicht-Feldeffektransistor。

    公开(公告)号:EP0000883A1

    公开(公告)日:1979-03-07

    申请号:EP78100594.7

    申请日:1978-08-04

    IPC分类号: H01L29/10 H01L29/78

    CPC分类号: H01L29/78 H01L29/7838

    摘要: Der Metalloxid-Silicium-Feldeffekttransistor weist im Kanalbereich eine vergrabene Isolierschicht (10) auf, die mit dem gleichen Dotierungsstoff dotiert ist, wie Source-und Drain-Zone, so dass die Verarmungsschichten der an der Ober- bzw. Untergrenze der Isolierschicht (10) gebildeten P-N-Übergänge (11, 13) sich in der Mitte der implantierten Isolierschicht (10) einander nähern, und so tatsächlich eine Isolierschicht zwischen Source und Drain darstellen. Die Anwesenheit dieser Schicht erhöht den Abstand zwischen den spiegelbildlich induzierten elektrostatischen Ladungen in der Gate-Elektrode und der Masse des Substrats unterhalb des MOSFETs, wodurch die Empfindlichkeit der Schwellwertspannung des Feldeffekttransistors für Veränderungen der Source-Substrat-Spannung herabgesetzt wird.

    摘要翻译: 1.一种具有第二导电类型的沟道区域(16)的绝缘层场效应晶体管,其形成在第一导电类型的源极(4)和漏极(6)之间,在第二导电类型的衬底(2)中,并且具有绝缘 栅极电极,其特征在于,在延伸到衬底(2)中的源极(4)和漏极(6)之间的沟道区(16)下面的衬底(2)中设置掩埋绝缘层(10) 出现与沟道区(16)相关的有效晶体管耗尽区,该层(10)可以通过施加临界衬底源极偏置Vscsc而被完全耗尽,由此栅电极和静电电极之间的静电电荷之间的距离 在衬底(2)中由它们引起的电荷增加到使得阈值电压VT相对于衬底源极偏置Vxs的变化的灵敏度降低的程度。