公开(公告)号：EP2018666B1

公开(公告)日：2011-04-06

申请号：EP07718446.3

申请日：2007-05-15

Applicant: AT & S Austria Technologie & Systemtechnik Aktiengesellschaft

Inventor： VORABERGER, Hannes ,  SCHMID, Gerhard ,  RIESTER, Markus ,  STAHR, Johannes

IPC: H01L23/498 ,  H05K1/18

CPC classification number: H01L23/498 ,  H01L21/4846 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01061 ,  H01L2924/01068 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K1/113 ,  H05K1/186 ,  H05K3/005 ,  H05K3/107 ,  H05K3/4644 ,  H05K3/465 ,  H05K3/4652 ,  H05K2201/09436 ,  H05K2201/10734 ,  Y10T29/4913 ,  H01L2924/00012 ,  H01L2924/00

Abstract: In a method for fixing an electronic component (3) on a printed circuit board (2), and contact-connecting the electronic component (3) to the printed circuit board (2), the following steps are provided: - providing the printed circuit board (2) having a plurality of contact and connection pads (8), - providing the electronic component (3) having a number of contact and connection locations (5) corresponding to the plurality of contact and connection pads (8) of the printed circuit board (2), with a mutual spacing reduced in comparison with the spacing of the contact and connection pads (8) of the printed circuit board (2), and – arranging or forming at least one interlayer (4) for routing the contact and connection locations (5) of the electronic component (3) between the contact and connection pads (8) of the printed circuit board (2) and the contact and connection locations (5) of the electronic component (3). A method for producing an interlayer (4) for routing and a system having a printed circuit board (2) and an electronic component (3) using the interlayer (4) for routing are also provided.

公开(公告)号：EP2192613A4

公开(公告)日：2011-03-16

申请号：EP08831960

申请日：2008-09-19

Applicant: NEC CORP

Inventor： YAMAZAKI TAKAO

IPC: H01L23/12 ,  H01L21/60 ,  H01L23/00 ,  H01L25/065 ,  H01L25/07 ,  H01L25/10 ,  H01L25/11 ,  H01L25/18

CPC classification number: H01L23/4985 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/5387 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/81001 ,  H01L2224/8112 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/83855 ,  H01L2224/8388 ,  H01L2224/92225 ,  H01L2225/1005 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/3511 ,  H05K1/189 ,  H05K2201/056 ,  H05K2201/10515 ,  H05K2201/10734 ,  H01L2924/07025 ,  H01L2924/00 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/00015 ,  H01L2224/0401

Abstract: There is provided a low-cost semiconductor device that commercial and quality-assured (inspected) chip size packages can be stacked and has a small co-planarity value and a high mounting reliability. A semiconductor device in which a flexible circuit substrate is adhered to at least a part of a lateral side of a semiconductor package, and the flexible circuit substrate, which is on a side facing solder balls of the semiconductor package, is folded at a region 25 inside of an edge of the semiconductor package and also at a region 26 outside of the outermost solder balls 24 on the semiconductor package

公开(公告)号：EP2064930B1

公开(公告)日：2010-11-10

申请号：EP07828864.4

申请日：2007-09-21

Applicant: Panasonic Corporation

Inventor： YOSHINAGA, Seiichi ,  WADA, Yoshiyuki ,  SAKAI, Tadahiko

IPC: H05K3/30 ,  H01L21/56

CPC classification number: H01L21/563 ,  H01L23/293 ,  H01L2224/73203 ,  H01L2924/15311 ,  H01L2924/3511 ,  H05K3/305 ,  H05K3/3436 ,  H05K2201/0133 ,  H05K2201/10734 ,  H05K2203/0545 ,  Y02P70/613 ,  Y10T428/23971 ,  Y10T428/31525

Abstract: The invention intends to provide an electronic component mounting structure where the repairability and the impact resistance are combined. In an electronic component mounting structure, a plurality of solder balls disposed in plane between an electronic component and a substrate is melted to bond the electronic component and the substrate and a resin of which tensile elongation after the curing is in the range of 5 to 40% is filled in portions that are gaps between the electronic component and the substrate and correspond to at least four corners of the electronic component to reinforce. Since the reinforcement area is small, the repairability such as the easy removability of the resin and the reusability of the substrate are excellent, the resin itself is allowed to expand to the impact at the drop to play a role of reinforcing the bonding without breaking, and the impact resistance is excellent as well.

公开(公告)号：EP2232964A1

公开(公告)日：2010-09-29

申请号：EP08862313.7

申请日：2008-12-03

Applicant: Micron Technology, Inc.

Inventor： LEE, Teck, Kheng

IPC: H05K3/40

CPC classification number: H01L24/14 ,  H01L21/4846 ,  H01L23/481 ,  H01L23/49811 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/1012 ,  H01L2224/13012 ,  H01L2224/13016 ,  H01L2224/13019 ,  H01L2224/13023 ,  H01L2224/1403 ,  H01L2224/16145 ,  H01L2224/73103 ,  H01L2224/73204 ,  H01L2224/81136 ,  H01L2224/81138 ,  H01L2224/8114 ,  H01L2224/81193 ,  H01L2224/812 ,  H01L2224/81208 ,  H01L2224/81801 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01028 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/20105 ,  H01L2924/20106 ,  H05K3/06 ,  H05K3/325 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/10674 ,  H05K2201/10734 ,  H05K2201/10977 ,  H05K2203/0315 ,  H05K2203/0369 ,  H05K2203/1476 ,  H01L2924/00012

Abstract: A method is disclosed which includes forming a layer of conductive material above a substrate, forming a masking layer above the layer of conductive material, performing a first etching process on the layer of conductive material with the masking layer in place, removing the masking layer and, after removing the masking layer, performing an isotropic etching process on the layer of conductive material to thereby define a plurality of piercing bond structures positioned on the substrate.

公开(公告)号：EP1854013A4

公开(公告)日：2010-09-08

申请号：EP06717412

申请日：2006-01-04

Applicant: XTREMEDATA INC

Inventor： BENBOW JAMES B ,  FINLEY GARY A ,  CHANDRAN RAVI V C ,  WOODS NATHAN A ,  KONONOV ROMAN

IPC: G06F13/14

CPC classification number: H05K1/141 ,  G06F1/184 ,  G06F1/185 ,  G06F1/186 ,  G06F15/7864 ,  H05K2201/049 ,  H05K2201/10212 ,  H05K2201/10704 ,  H05K2201/10734

公开(公告)号：EP1650804A3

公开(公告)日：2010-09-08

申请号：EP05028092.4

申请日：2002-02-15

Applicant: HITACHI, LTD.

Inventor： Sasakura, Takahiro Hitachi, Ltd. Int. Prop. Office ,  Abe, Seiichi Hitachi, Ltd. Intell. Prop. Office

IPC: H01L25/10 ,  H01L25/16 ,  H01L25/065 ,  H01L23/58

CPC classification number: H05K1/181 ,  H01L23/13 ,  H01L23/24 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/467 ,  H01L23/552 ,  H01L24/48 ,  H01L24/49 ,  H01L25/105 ,  H01L25/162 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49109 ,  H01L2225/1029 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15321 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3025 ,  H05K1/0262 ,  H05K1/141 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10689 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: In the past, a power supply distance between a power source and an LSI package could not be shortened and power supply variations could easily produce an adverse effect. In the present invention, a power supply module 11 is mounted on the surface of an LSI package 13. The power supply distance between the LSI 19 and power supply module 11 can be shortened. As a result, the power source noise can be reduced, the efficiency and response rate of the power source unit are high, and the generated electromagnetic field can be reduced. Moreover, since each LSI package has a power supply module required therefor, the number of required power source types (voltage types) on the substrate with the package mounted thereon can be decreased. As a result, the mounting efficiency can be increased and the substrate can be manufactured at a low cost.

公开(公告)号：EP1723654B1

公开(公告)日：2010-06-30

申请号：EP05713488.4

申请日：2005-02-14

Applicant: Intel Corporation

Inventor： SPRIETSMA, John ,  BAINS, Kuljit ,  LEDDIGE, Michael

IPC: G11C5/00

CPC classification number: H01L23/49816 ,  G11C5/02 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/16225 ,  H05K1/181 ,  H05K2201/10159 ,  H05K2201/10734 ,  H05K2203/1572 ,  Y02P70/611

公开(公告)号：EP2192613A1

公开(公告)日：2010-06-02

申请号：EP08831960.3

申请日：2008-09-19

Applicant: Nec Corporation

Inventor： YAMAZAKI, Takao

IPC: H01L23/12 ,  H01L25/065 ,  H01L25/07 ,  H01L25/10 ,  H01L25/11 ,  H01L25/18

CPC classification number: H01L23/4985 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/5387 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/81001 ,  H01L2224/81011 ,  H01L2224/8112 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/83855 ,  H01L2224/8388 ,  H01L2224/92225 ,  H01L2225/1005 ,  H01L2225/107 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/3511 ,  H05K1/189 ,  H05K2201/056 ,  H05K2201/10515 ,  H05K2201/10734 ,  H01L2924/07025 ,  H01L2924/00 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/00015 ,  H01L2224/0401

Abstract: There is provided a low-cost semiconductor device that commercial and quality-assured (inspected) chip size packages can be stacked and has a small co-planarity value and a high mounting reliability. A semiconductor device in which a flexible circuit substrate is adhered to at least a part of a lateral side of a semiconductor package, and the flexible circuit substrate, which is on a side facing solder balls of the semiconductor package, is folded at a region 25 inside of an edge of the semiconductor package and also at a region 26 outside of the outermost solder balls 24 on the semiconductor package

Abstract translation: 提供了一种低成本的半导体器件，其可以堆叠商业和质量保证（检查）的芯片尺寸封装，并且具有小的共面性值和高安装可靠性。 一种半导体器件，其中柔性电路衬底被粘附到半导体封装的侧面的至少一部分，并且柔性电路衬底在面向半导体封装的焊球的一侧上在区域25 位于半导体封装的边缘内并且还位于半导体封装上的最外面的焊球24外侧的区域26处

公开(公告)号：EP1777745A3

公开(公告)日：2010-05-05

申请号：EP06019654.0

申请日：2006-09-20

Applicant: E.I. DU PONT DE NEMOURS AND COMPANY

Inventor： Borland, William J. ,  Ferguson, Saul

IPC: H05K1/16 ,  H01L23/50 ,  H01L23/498

CPC classification number: H01L23/49822 ,  H01L23/49838 ,  H01L23/50 ,  H01L2224/16 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K1/113 ,  H05K1/162 ,  H05K2201/09309 ,  H05K2201/09763 ,  H05K2201/10734

Abstract: A device comprising a power core wherein said power core comprises: at least one embedded singulated capacitor layer containing at least one embedded singulated capacitor (240) wherein said embedded singulated capacitor comprises at least a first electrode and a second electrode and wherein said embedded singulated capacitor is positioned on the outer layer of the power core with both first and second electrodes of the capacitor on the outer layer of the power core so that at least one Vcc (power) terminal and at least one Vss (ground) terminal of a semiconductor device (201) can be directly connected to at least one first and at least one second electrode, respectively.

公开(公告)号：EP1515365B1

公开(公告)日：2010-03-31

申请号：EP04025966.5

申请日：2001-07-26

Applicant: Intel Corporation

Inventor： Chakravorty, Kishore

IPC: H01L23/498 ,  H05K1/16

CPC classification number: H01L23/50 ,  H01L23/49822 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/15311 ,  H05K1/0306 ,  H05K1/112 ,  H05K1/162 ,  H05K1/185 ,  H05K3/4611 ,  H05K3/4629 ,  H05K3/4688 ,  H05K2201/0187 ,  H05K2201/049 ,  H05K2201/10674 ,  H05K2201/10734 ,  H01L2224/05599