公开(公告)号：EP3739497A3

公开(公告)日：2021-03-24

申请号：EP20184634.2

申请日：2018-12-13

Applicant: TactoTek Oy

Inventor： SINIVAARA, Hasse ,  HEIKKILÄ, Tuomas ,  KERÄNEN, Antti

IPC: G06F30/398 ,  B29C64/112 ,  B29C64/393 ,  B29K101/12 ,  B29L31/34 ,  B33Y10/00 ,  B33Y50/02 ,  G06F30/36 ,  G06F30/392 ,  G06F119/18 ,  G06F115/12

Abstract: An electronic arrangement for facilitating circuit layout design in connection with target designs, the arrangement including at least one communication interface for transferring data, at least one processor for processing instructions and other data, and a memory for storing the instructions and other data. The at least one processor being configured, in accordance with the stored instructions, to cause: obtaining and storing information in a data repository hosted by the memory, receiving design input characterizing target design to be produced from a substrate, determining a mapping between locations of the target design and the substrate, and establishing and providing digital output comprising human and/or machine readable instructions indicative of the mapping to a receiving entity, such as a manufacturing equipment, e.g. printing, electronics assembly and/or forming equipment.