公开(公告)号：EP0440142A3

公开(公告)日：1996-09-18

申请号：EP91101090.8

申请日：1991-01-28

申请人： YOZAN INC. ,  SHARP KABUSHIKI KAISHA

发明人： Kumagai, Ryohei, c/o Ezel Inc.

IPC分类号： G07D7/00

CPC分类号： G07D7/12 ,  G07D7/20

摘要： An image verification system for verifying a sample image and a reference image registered beforehand, comprising; a means for storing a relationship between the sample and the reference image when the sample image corresponds to the reference image; and a means for judging if the sample image corresponds to the reference image by verifying the sample one and the reference one according to the relationship between characteristics values of the sample and reference one.

公开(公告)号：EP0707276A1

公开(公告)日：1996-04-17

申请号：EP95115334.5

申请日：1995-09-28

申请人： YOZAN INC. ,  SHARP KABUSHIKI KAISHA

发明人： Shou, Guoliang, c/o Yozan Inc. ,  Motohashi, Kazunori, c/o Yozan Inc. ,  Yamamoto, Makoto, c/o Yozan Inc. ,  Takatori, Sunao, c/o Yozan Inc.

IPC分类号： G06J1/00

CPC分类号： G06J1/00

摘要： An interface circuit comprising a digital to analog converter which comprises a register for receiving and holding each bit of a digital signal, a capacitive coupling for integrating total bits held in the register with weighting, an inverted amplifier circuit for receiving an output of the capacitive coupling and for outputting an analog output voltage, and a feedback capacitance for connecting an outputs of the inverted amplifier circuit to an input of the inverted amplifier circuit, an analog signal line to which the analog output voltage is connected, and an analog to digital converter which comprises a plurality thresholding circuits with stepwise thresholds to which the analog signal line is commonly inputted, each the thresholding circuit receiving outputs of the thresholding circuits of higher threshold with weighting so that the thresholding circuits repeatedly change the outputs from high level to low level or from low level to high level.

摘要翻译： 一种接口电路，包括数模转换器，其包括用于接收和保持数字信号的每一位的寄存器，用于将保持在寄存器中的总比特积分为加权的电容耦合，用于接收电容耦合的输出的反相放大器电路 并且用于输出模拟输出电压，以及用于将反相放大器电路的输出连接到反相放大器电路的输入的反馈电容，连接有模拟输出电压的模拟信号线以及模数转换器， 包括具有逐步阈值的多个阈值电路，模拟信号线被共同输入，每个阈值电路接收具有加权的较高阈值的阈值电路的输出，使得阈值电路重复地将输出从高电平改变为低电平或从 低水平到高水平。

公开(公告)号：EP0707275A1

公开(公告)日：1996-04-17

申请号：EP95115333.7

申请日：1995-09-28

申请人： YOZAN INC. ,  SHARP KABUSHIKI KAISHA

发明人： Shou, Guoliang, c/o Yozan Inc. ,  Motohashi, Kazunori, c/o Yozan Inc. ,  Yamamoto, Makoto, c/o Yozan Inc. ,  Takatori, Sunao, c/o Yozan Inc.

IPC分类号： G06J1/00

CPC分类号： G06J1/00

摘要： A multiplication circuit comprises a plurality of the first switching means for receiving a common analog input voltage and a reference voltage and for alternatively outputting the input voltage or the reference voltage, the first capacitive coupling with a plurality of capacitances for receiving outputs of the first switching means are inputted, the first inverted amplifier for receiving an output of the first capasitive coupling, an output of the first inverted amplifier being fed back to its input; the second inverted amplifier for receiving the output of the first inverted amplifier, an output of the second inverted amplifier being fed back to its inputand characterized in that one or more of the capacitances in the first capacitive coupling is connected to the second capacitive coupling with a plurality of capacitances and that a plurality of the second switching means are connected to each capacitances of the second capacitive coupling, the second switching means alternatively outputting the analog input voltage or the reference voltage.

摘要翻译： 乘法电路包括多个第一开关装置，用于接收公共模拟输入电压和参考电压，并用于交替输出输入电压或参考电压，第一电容耦合具有多​​个电容，用于接收第一开关的输出 装置被输入，第一反相放大器用于接收第一无感耦合的输出，第一反相放大器的输出被反馈到其输入端; 所述第二反相放大器用于接收所述第一反相放大器的输出，所述第二反相放大器的输出被反馈到其输入端，并且其特征在于，所述第一电容耦合中的一个或多个电容连接到所述第二电容耦合， 多个电容并且多个第二开关装置连接到第二电容耦合的每个电容，第二开关装置可选地输出模拟输入电压或参考电压。

公开(公告)号：EP0704904A1

公开(公告)日：1996-04-03

申请号：EP95115448.3

申请日：1995-09-29

申请人： YOZAN INC. ,  SHARP KABUSHIKI KAISHA

发明人： Shou, Guoliang, c/o Yozan Inc. ,  Motohashi, Kazunori, c/o Yozan Inc. ,  Yamahoto, Makoto, c/o Yozan Inc. ,  Takatori, Sunao, c/o Yozan Inc.

IPC分类号： H01L27/08 ,  H01L27/10

CPC分类号： H01L27/0805 ,  H01L27/101

摘要： A capacitance forming method for forming capacitances corresponding to a plurality of constant numbers within a large scale integrated circuit (LSI) comprises steps of defining a unit capacitance with a predetermined shape, defining an arrangement of a plurality of the unit capacitances of a number necessary for total capacity of capacitances to be formed in two dimension in an area of the LSI, selecting the unit capacitances of a number corresponding to the maximal capacity among capacities of the capacitances to be formed so that the selected unit capacitances are equivalently dispersed over the area, and successively selecting other of the capacitances than the capacitance of the maximal capacity in the order of capacities, and selecting the unit capacitances of a number corresponding to a capacity of each the capacitance selected so that the selected unit capacitances are equivalently dispersed over an area of the rest of the unit capacitances which have not selected yet.

摘要翻译： 用于在大规模集成电路（LSI）内形成对应于多个常数的电容的电容形成方法包括以预定形状定义单位电容的步骤，限定多个单位电容的排列， 在LSI的区域中形成二维电容的总容量，选择与要形成的电容的容量之间的最大容量对应的数字的单位电容，使得所选择的单位电容等效地分散在该区域上， 并且依次选择容量级别中最大容量的电容以外的其他电容，并且选择与所选择的每个电容的容量对应的数量的单位电容，使得所选择的单位电容等价地分散在 剩余的单位电容尚未选择。

公开(公告)号：EP0375805B1

公开(公告)日：1995-05-24

申请号：EP88121903.4

申请日：1988-12-30

申请人： YOZAN INC. ,  SHARP KABUSHIKI KAISHA

发明人： Kumagai, Ryohei

IPC分类号： G06T9/20

CPC分类号： G06T9/20 ,  G06K9/481

公开(公告)号：EP0585861A3

公开(公告)日：1994-12-14

申请号：EP93113849.9

申请日：1993-08-30

申请人： YOZAN INC. ,  SHARP KABUSHIKI KAISHA

发明人： Shou, Guoliang, c/o Yozan Inc. ,  Takatori,Sunao, c/o Yozan Inc. ,  Yamamoto, Makoto c/o Yozan Inc.

IPC分类号： G06K9/64

CPC分类号： G06K9/6203

摘要： A plurality of successive pixels of a template and corresponding pixels of an input image inputted into a hardware with a function of multiplication, addition and subtraction. A summation of differences is calculated by the hardware between the corresponding pixels of template and input image, and written into a work memory. An image verification is performed by integrating successive results of the summation for the total area to be verified in high speed with utilizing a general purpose image processing hardware, without using a special purpose image processing hardware.

公开(公告)号：EP0584688A3

公开(公告)日：1994-04-06

申请号：EP93113106.4

申请日：1993-08-16

申请人： YOZAN INC. ,  SHARP KABUSHIKI KAISHA

发明人： Shou, Guoliang ,  Takatori, Sunao ,  Yamamoto, Makoto

IPC分类号： G11C11/412

CPC分类号： G11C11/412

摘要： The present invention has an object to provide a memory device without the necessity of refreshment, whose circuit is small size. The memory device has a memory cell "MC" comprising: i) the first FET of P-channel having a gate "G1" connected input voltage "Vi" and source "S1" grounded through protect resistance "R1"; ii) the second FET of N-channel having a gate "G2" connected to a drain "D1" of the first FET, a drain "D2" connected to power source "Vcc", and a source "S2" connected to a gate "G1" of the first FET through protect resistance "R2"; and
   iii) a switch "SWR" connecting the gate "G2" of the second FET and power source "Vcc". Self-holding circuit is formed by the pair of FETs.

公开(公告)号：EP0584688A2

公开(公告)日：1994-03-02

申请号：EP93113106.4

申请日：1993-08-16

申请人： YOZAN INC. ,  SHARP KABUSHIKI KAISHA

发明人： Shou, Guoliang ,  Takatori, Sunao ,  Yamamoto, Makoto

IPC分类号： G11C11/412

CPC分类号： G11C11/412

摘要： The present invention has an object to provide a memory device without the necessity of refreshment, whose circuit is small size.
The memory device has a memory cell "MC" comprising: i) the first FET of P-channel having a gate "G1" connected input voltage "Vi" and source "S1" grounded through protect resistance "R1"; ii) the second FET of N-channel having a gate "G2" connected to a drain "D1" of the first FET, a drain "D2" connected to power source "Vcc", and a source "S2" connected to a gate "G1" of the first FET through protect resistance "R2"; and
   iii) a switch "SWR" connecting the gate "G2" of the second FET and power source "Vcc". Self-holding circuit is formed by the pair of FETs.

摘要翻译： 本发明的一个目的是提供一种不需要刷新，其电路尺寸小的存储器件。 该存储器件具有一个存储单元“MC”，该存储单元包括：i）具有通过保护电阻“R1”接地的输入电压“Vi”和源“S1”接地的栅极“G1”的P沟道第一FET; ii）具有连接到第一FET的漏极“D1”的栅极“G2”，连接到电源“Vcc”的漏极“D2”和连接到栅极的源极“S2”的N沟道的第二FET 第一个FET的“G1”通过保护电阻“R2”; 和iii）连接第二FET的栅极“G2”和电源“Vcc”的开关“SWR”。 自保持电路由一对FET形成。

公开(公告)号：EP0577080A1

公开(公告)日：1994-01-05

申请号：EP93110372.5

申请日：1993-06-29

申请人： YOZAN INC.

发明人： Matsumoto, Koji, c/o Ezel Inc.

IPC分类号： H05K13/08 ,  H01L21/00

CPC分类号： H01L21/681 ,  H05K13/08

摘要： The present invention has a purpose to provide an inspection method of inclination of an IC in order to fix a position of IC speedily and precisely without the image information of binarized images.
An inspection method of inclination of an IC according to this invention defines an inspection area including open ends of IC pins, extracts longitudinal edges and open ends of pin of each IC pin from a density projection of each inspection area, calculates a representative point of each inspection area on a line along the open ends and calculates a center and inclination of an IC according to a difference of coordinates of a representative point of the inspection area positioninig in the opposite side.

摘要翻译： 本发明的目的是提供一种IC的倾斜检查方法，以便在没有二值化图像的图像信息的情况下快速且精确地固定IC的位置。 根据本发明的IC的倾斜检查方法定义了包括IC引脚的开口端的检查区域，从每个检查区域的密度投影中提取每个IC引脚的引脚的纵向边缘和开口端，计算每个IC引脚的代表点 检查区域沿着开口端的一条线上，并根据相对侧的检查区域位置的代表点的坐标差来计算IC的中心和倾斜度。

公开(公告)号：EP0573968A1

公开(公告)日：1993-12-15

申请号：EP93109220.9

申请日：1993-06-08

申请人： YOZAN INC.

发明人： Matsumoto, Koji

IPC分类号： H05K13/08

CPC分类号： H05K13/08

摘要： The present invention has a purpose to provide an inspection method of inclination of an IC in order to decide a position of IC speedily and precisely without the image information of binarized images or an image of each pin.
An inspection method of inclination of an IC for arranging sides of it approximately in parallel to X-axis and Y-axis comprising steps of: inputting image of an IC; defining a plurality of checking areas including open ends of a plurality of IC pins at predetermined positions in the image; generating a density projection along a direction parallel to IC pins expected in each checking area; regarding a position of the maximum value of a primary differential as the open ends of the IC pins; defining a representative point at a predetermined position on a line along the open ends; and calculating inclination of an IC according to the inclination of a reference line substantially connecting the representative points of the checking areas.

摘要翻译： 本发明的目的是提供IC的倾斜检查方法，以便在没有二值化图像的图像信息或每个引脚的图像的情况下快速且精确地确定IC的位置。 一种IC的倾斜检查方法，用于将其大致平行于X轴和Y轴的侧面布置，包括以下步骤：输入IC的图像; 定义多个检查区域，包括在图像中的预定位置处的多个IC引脚的开口端; 沿着平行于每个检查区域中的IC引脚的方向产生密度投影; 关于作为IC引脚的开路端的初级差分的最大值的位置; 在沿所述开放端的一条线上的预定位置处限定代表点; 以及根据基本上连接检查区域的代表点的参考线的倾斜度来计算IC的倾斜度。