-
31.发明公开Discrete increment signal processing system and method using parallel branched N-state networks 失效离散增量信号处理系统和使用并行分支的N状态网络的方法
公开(公告)号：EP0408323A3
公开(公告)日：1991-10-02
申请号：EP90307557.0
申请日：1990-07-10
发明人： Pritchett, Samuel D.
摘要： A parallel branched N-state design method is used for discrete increment signal processing systems, such as incremental phase shifters and attenuators. These systems are implemented using parallel branched signal processing networks, each with N parallel discrete increment branch circuits (i.e., without being restricted to binary-state networks). In comparison with conventional cascaded binary-state networks, the parallel branched N-state design achieves reduced complexity and insertion loss. An exemplary embodiment of a phase shift system providing 32 phase increments (or states) uses three cascaded phase shift networks -- two quaternary-state networks (Quits 10, 20) and a single binary-state network (Bit 30). The most significant Quit (10) illustrates the N-state design, providing the four most significant phase states (reference, +90°, -180°, -90°) using four switched-line branch circuits (100, 200, 300, 400), each controlled by two PIN diode control elements (D1A/D1B, D2A/D2B, D3A/D3B, D4A/D4B). A parallel branched N-state design for discrete increment systems minimizes insertion loss and complexity by minimizing the total number of cascaded networks, the total number of cascaded branch circuits and the total number of branch control elements.
搜索结果
31 条记录 (耗时 0.006 秒)
