公开(公告)号：EP3314835A1

公开(公告)日：2018-05-02

申请号：EP16815512.5

申请日：2016-06-27

申请人： Kandou Labs S.A.

发明人： HORMATI, Ali ,  TAJALLI, Armin ,  SHOKROLLAHI, Amin

IPC分类号： H04L27/26

摘要： Transmission of baseband and carrier-modulated vector codewords, using a plurality of encoders, each encoder configured to receive information bits and to generate a set of baseband-encoded symbols representing a vector codeword; one or more modulation circuits, each modulation circuit configured to operate on a corresponding set of baseband-encoded symbols, and using a respective unique carrier frequency, to generate a set of carrier-modulated encoded symbols; and, a summation circuit configured to generate a set of wire-specific outputs, each wire-specific output representing a sum of respective symbols of the carrier-modulated encoded symbols and at least one set of baseband-encoded symbols.

公开(公告)号：EP3175592A1

公开(公告)日：2017-06-07

申请号：EP15827077.7

申请日：2015-08-03

申请人： Kandou Labs S.A.

发明人： HOLDEN, Brian ,  SHOKROLLAHI, Amin

IPC分类号： H04L25/49

CPC分类号： H04L27/2637 ,  G06F13/426 ,  G11C7/1006 ,  G11C7/1066 ,  G11C7/1093 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4093 ,  H04L25/4919 ,  Y02D10/14 ,  Y02D10/151

摘要： Orthogonal differential vector signaling codes are described which support encoded sub-channels allowing transport of distinct but temporally aligned data and clocking signals over the same transport medium. Embodiments providing enhanced LPDDR interfaces are described which are suitable for implementation in both conventional high-speed CMOS and DRAM integrated circuit processes.

摘要翻译： 描述了正交差分向量信令代码，其支持经编码的子信道，允许在相同的传输介质上传输不同但时间上对齐的数据和时钟信号。 描述了提供增强型LPDDR接口的实施例，其适用于传统的高速CMOS和DRAM集成电路工艺。

公开(公告)号：EP3111607A1

公开(公告)日：2017-01-04

申请号：EP15710999.2

申请日：2015-03-02

申请人： Kandou Labs S.A.

发明人： HOLDEN, Brian ,  SHOKROLLAHI, Amin ,  SIMPSON, Richard

IPC分类号： H04L25/49

摘要： Vector signaling codes providing guaranteed numbers of transitions per unit transmission interval are described, along with methods and systems for their generation and use. The described architecture may include multiple communications sub-systems, each having its own communications wire group or sub-channel, clock-embedded signaling code, pre- and post-processing stages to guarantee the desired code transition density, and global encoding and decoding stages to first distribute data elements among the sub-systems, and then to reconstitute the received data from its received sub-system elements.

摘要翻译： 描述了每单位传输间隔提供保证数量的转换的矢量信令代码，以及用于其生成和使用的方法和系统。 所描述的架构可以包括多个通信子系统，每个子系统具有其自己的通信线组或子信道，时钟嵌入式信令代码，预处理和后处理阶段以保证期望的代码转换密度，以及全局编码和解码阶段 首先在子系统之间分配数据元素，然后从接收到的子系统元素重构接收到的数据。