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43 条记录 (耗时 0.012 秒)

    Memory array
    42.
    发明公开
    Memory array 失效
    矩阵存储器。

    公开(公告)号：EP0071042A2

    公开(公告)日：1983-02-09

    申请号：EP82105997.9

    申请日：1982-07-06

    申请人： International Business Machines Corporation

    发明人： Malaviya, Shashi Dhar

    IPC分类号： G11C11/34

    CPC分类号： G11C11/34 ,  H01L27/1025

    摘要： An electronic data storage or memory array having DC stable memory cells which utilize the principle of a unique substrate biasing mechanism, whereby a channel region defined by resistive substrate material and formed under a controlled electrode (20) becomes "pinched off' and, in the process, so affects the DC potential at that electrode as to maintain the pinched off condition. Consequently, the memory cell becomes established in a first DC stable state ("one" state). The principle is preferably embodied in a field effect transistor (22), the resistive channel region being connected in a DC conductive path to a fixed resistor (R1) and a potential source (+V). Accordingly, when appropriate signal levels representing a binary "one" are applied to word and bit lines (WL1, BL1) connected to a first controlling, or gate, electrode and to a second controlling electrode, respectively, of the FET, the described pinch-off occurs, with concomitantly high resistance (R2) in the DC path, such that the potential adjacent the controlled electrode (20) is maintained in the "one" state that was initiated by the signals on the word and bit lines. On the other hand, when signals representing a "zero" are applied to the same controlling electrodes, the resistive channel region (R2) under the controlled electrode (20) is no longer pinched-off, whereby the memory cell becomes established in the second or "zero" DC stable state. Means for reading the stored data in the cell are integrated with the cell.

    Halbleiterspeichermatrix mit statischen Speicherzellen
    43.
    发明公开
    Halbleiterspeichermatrix mit statischen Speicherzellen 失效
    Halbleiterspeichermatrix mit statischen Speicherzellen。

    公开(公告)号：EP0031492A2

    公开(公告)日：1981-07-08

    申请号：EP80107620.9

    申请日：1980-12-04

    申请人： International Business Machines Corporation

    发明人： Malaviya, Shashi Dhar

    IPC分类号： G11C11/40 ,  G11C7/00

    CPC分类号： G11C17/08 ,  G11C11/4116

    摘要： In einem bipolaren Halbleiterspeicher mit statischen Speicherzellen aus zwei kreuzgekoppelten Transistoren ist der Emittor jedes Transistors mit einer Bitleitung verbunden. Die Bitleitungen sind mit Abfühlverstärkern geringer Impedanz verbunden, wobei die Verstärkerausgänge miteinander verbunden sind. Dieser Verbindungspunkt ist mit einer Stromquelle verbunden. Durch die niederohmige Verbindung zwischen den Emittoren der beiden Zellentransistoren wird eine alternative Verwendung des Speichers als Festwertspeicher erleichtert.

    摘要翻译： 1.一种半导体存储矩阵，包括由字线，一对位线之间的两个交叉耦合晶体管组成的静态存储单元，所述单元晶体管的各个发射极连接到一个相应的位线，其特征在于，所述两个位线 20,21）分别连接到发射器彼此连接并且连接到公共电流源（61,60）的较低阻抗的两个感测晶体管（58,59）的集电极。