公开(公告)号：EP0585619B1

公开(公告)日：2000-03-08

申请号：EP93112254.3

申请日：1993-07-30

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Bosshart, Patrick W. ,  Agarwala, Sanjive

IPC分类号： G06F7/00 ,  G06F7/02 ,  G06F9/30

CPC分类号： G06F7/505 ,  G06F7/02 ,  G06F7/49905 ,  G06F9/30094

公开(公告)号：EP0590914B1

公开(公告)日：1999-11-17

申请号：EP93307644.0

申请日：1993-09-27

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Bosshart, Patrick W.

IPC分类号： G06F9/26 ,  G06F9/32

CPC分类号： G06F7/507 ,  G06F9/30094 ,  G06F9/3844

公开(公告)号：EP0820147A2

公开(公告)日：1998-01-21

申请号：EP97305362.2

申请日：1997-07-17

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Bosshart, Patrick W.

IPC分类号： H03K19/096

CPC分类号： H03K19/0963

摘要： In a preferred logic circuit embodiment (10), there is a precharge node (14) coupled to be precharged to a precharge voltage (V DD ) during a precharge phase and operable to be discharged during an evaluate phase. The circuit also includes a conditional series discharge path (22, 24, and 16) connected to the precharge node and operable to couple the precharge node to a voltage different than the precharge voltage. The conditional series discharge path includes a low threshold voltage transistor (22 or 24) having a first threshold voltage, and a high threshold voltage transistor (16) having a second threshold voltage higher in magnitude than the first threshold voltage, wherein a voltage connected to a gate of the high threshold voltage transistor is disabling during the precharge phase.

摘要翻译： 在优选逻辑电路实施例（10）中，存在预充电节点（14），其在预充电阶段期间被耦合以预充电到预充电电压（VDD），并且可以在评估阶段期间被放电。 电路还包括连接到预充电节点并且可操作以将预充电节点耦合到不同于预充电电压的电压的条件串联放电路径（22,24和16）。 条件串联放电路径包括具有第一阈值电压的低阈值电压晶体管（22或24）和具有比第一阈值电压更高的第二阈值电压的高阈值电压晶体管（16），其中连接到 高阈值电压晶体管的栅极在预充电阶段期间禁用。

公开(公告)号：EP0585619A3

公开(公告)日：1994-08-10

申请号：EP93112254.3

申请日：1993-07-30

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Bosshart, Patrick W. ,  Agarwala, Sanjive

IPC分类号： G06F9/30 ,  G06F7/00

CPC分类号： G06F7/505 ,  G06F7/02 ,  G06F7/49905 ,  G06F9/30094

摘要： An arithmetic or logical computation result detection circuit (60) is described. The circuit has a set of one-bit-zero cells (62) which receive a first operand, A, a second operand, B, and a C in , and generates a set of one-bit-zero signals, Z. A combinatorial circuit (64) receives the set of one-bit-zero signals and provides a selected output which is a known function of the one-bit-zero signals. In a preferred embodiment, the combinatorial circuit (64) is a logical AND function which detects a condition when all the one-bit-zero signals are positively asserted. In various embodiments of the preferred invention the one-bit-zero signals may be operable to detect an arithmetic zero condition for operations of addition, subtraction, or a logic operation. Other devices, systems and methods are also disclosed.

公开(公告)号：EP0279953A3

公开(公告)日：1990-01-31

申请号：EP87119350.4

申请日：1987-12-30

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Bosshart, Patrick W.

IPC分类号： G06F9/26 ,  G06F9/28

CPC分类号： G06F9/28 ,  G06F9/26 ,  G06F9/3017 ,  G06F9/30189

摘要： A computer system uses microcode subroutines to execute complex macroinstruction. Each macroinstruction is used to index a table (18). Simple macroinstructions have a single microinstruction counterpart in the table (18), and such microinstruction is performed directly in order to execute that macroinstruction. The table entry corresponding to more complex macroinstructions is a jump microinstruction, with the target of the microcode jump being an appropriate subroutine in microcode memory (16).

公开(公告)号：EP0180369A3

公开(公告)日：1988-03-16

申请号：EP85307393

申请日：1985-10-15

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Bosshart, Patrick W.

IPC分类号： G06F12/08

CPC分类号： G06F12/126 ,  G06F12/0864 ,  G06F12/1045

摘要： A cache memory addressable by both physical and virtual addresses includes a cache data memory (64) and a tag memory (66). The tag memory (66) is comprised of a virtual tag memory (68) and a physical tag memory (70). The physical and virtual tag memories are both addressable by the least significant bits (LSB) of the address signal to output tag portions of addresses associated with data stored in the cache data memory (64). A switch (78) selects between the outputs from the memories (68) and (70) under control of an arbitration unit (88). The arbitration unit (88) distinguishes between virtual or physical addresses input thereto. A comparator (100) compares the selected tag portion with the tag portion of the received address to determine if a match exists. If a match exists, the output of the cache data memory is selected with a switch (84).