公开(公告)号：EP0067031A1

公开(公告)日：1982-12-15

申请号：EP82302831.1

申请日：1982-06-02

申请人： Amm, Ronald Mervyn

发明人： Amm, Ronald Mervyn

IPC分类号： F02B17/00 ,  F02B19/06

CPC分类号： F02B19/06 ,  F02B3/06 ,  F02B17/00 ,  F02B75/04 ,  Y02T10/125

摘要： An engine includes an engine block (10) provided with cylinders (12, 14) having two pistons (16, 18) and a cylinder head (19) having a piston (20) biased by means of torsion bars (24). The biased piston (20) is held in position by an arm (22) which is restrained by torsion bars (24). During the compression stroke of the engine the biased piston (20) is seated with faces (30, 32), in contact and on ignition of the compressed mixture the biased piston (20) is lifted off the seat (32) creating a common combustion chamber in which separate charges are mixed. The biased piston (20) limits the combustion space and thereby controls the compression ratio to suit the desired performance.

公开(公告)号：EP0064819A1

公开(公告)日：1982-11-17

申请号：EP82301963.3

申请日：1982-04-16

申请人： Oki Electric Industry Company, Limited ,  NIPPON HOSO KYOKAI

发明人： Ohta, Tomozo c/o Oki Electric Industry Co., Ltd ,  Tsutsumi, Yoshio Oki Electric Industry Co.,Ltd. ,  Konishi, Yoshihiro c/o Nippon Hoso Kyokai

IPC分类号： H03D3/00

CPC分类号： H03D3/00 ,  H03G5/24

摘要： An FM signal demodulation system comprises a signal level detector (1), an adaptive bandpass filter (2), a frequency discriminator (3), amplifiers and amplitude limiters (4,5), and a fixed-bandwidth reference bandpass filter (8). The FM signal is fed to an input terminal (6) and the demodulated output is obtained from an output terminal (7).
The threshold level for demodulating the FM signal, for example a television picture signal, is improved by restricting the bandwidth of the signal using the adaptive bandpass filter (2), thereby improving the picture quality and/or the signal/noise ratio of the demodulated signal. The adaptive bandpass filter has a wide bandwidth when the signal level is sufficiently higher than the threshold level, but a narrow bandwidth when the signal level is close to or lower than the threshold level. The bandwidth of the adaptive bandpass filter is adjusted according to the total power of the input FM signal, or the carrier signal to noise ratio.

摘要翻译： FM信号解调系统包括信号电平检测器（1），自适应带通滤波器（2），鉴频器（3），放大器和限幅器（4,5）和固定带宽参考带通滤波器（8） 。 FM信号被馈送到输入端（6），并且从输出端（7）获得解调输出。 ...通过使用自适应带通滤波器（2）限制信号的带宽来提高用于解调FM信号（例如电视图像信号）的阈值电平，从而提高图像质量和/或信号/ 解调信号的噪声比。 当信号电平足够高于阈值电平时，自适应带通滤波器具有宽带宽，而当信号电平接近或低于阈值电平时，具有窄带宽。 根据输入FM信号的总功率或载波信噪比，自适应带通滤波器的带宽进行调整。

公开(公告)号：EP0061271A1

公开(公告)日：1982-09-29

申请号：EP82301274.5

申请日：1982-03-12

申请人： FUJITSU LIMITED

发明人： Takemae, Yoshihiro ,  Nakano, Tomio ,  Ohira, Tsuyoshi

IPC分类号： G11C11/24

CPC分类号： G11C11/4093

摘要： A semiconductor memory device comprises an output buffer circuit (16) which receives data signals (RD, RD) read out from a memory cell array (11, 12), an output stage MOS transistor (17) which is turned ON and OFF according to the output signals of the output buffer circuit, and an OBE (output buffer enable) signal generator circuit (19) for generating an OBE signal which is used as the voltage supply to the output stage of the output buffer circuit. A circuit (20) is provided for generating a voltage V BS which is higher than the supply voltage V CC before the rise of the OBE signal. The voltage V BS is used as a voltage supply to the output stage of the OBE signal generator circuit, whereby the OBE signal is formed as a voltage waveform which rises rapidly to a level which is higher than the supply voltage V CC . This speeds up the rise time of the data output D out from the output stage (17), and hence decreases the access time of the memory device.

公开(公告)号：EP0047114A1

公开(公告)日：1982-03-10

申请号：EP81303831.2

申请日：1981-08-21

申请人： FANUC LTD.

发明人： Inaba, Hajimu ,  Miyashita, Hideo

IPC分类号： H04L1/22 ,  G05B23/02 ,  G01R31/02 ,  G05B19/42 ,  B25J9/18

CPC分类号： G05B9/03 ,  B25J9/161 ,  G05B19/4063 ,  G05B2219/33253 ,  G05B2219/36159 ,  H04L1/22

摘要： A circuit for switching transmission lines and capable of detecting an interruption in the transmission lines comprises a plurality of pairs of transmission lines (24) which can transmit sets of digital signals with an opposite polarity to each other. A plurality of drivers (D 1 ,D 2 ---D n ) feed the signals to the transmission lines and a plurality of receivers (R 1 ,R 2 ---R n ) receive the transmitted signals. A plurality of AND gates (A 1 ,A 2 ---A n ) receive outputs from the receivers and an OR gate (23) receives the outputs from the AND gates. A respective exclusive-OR gate(31) is connected to each pair of transmission lines, and a respective filter (32) receives the output from each exclusive-OR gate and drives the respective AND gate. Thereby, when a transmission line (24) is interrupted, detection of the interrupted transmission line is carried out, and the transmission line is switched out so that the transmitted signal is not interrupted.

摘要翻译： 用于切换传输线并且能够检测传输线路中断的电路包括多对传输线路（24），它们可以发送彼此相反极性的数字信号组。 多个驱动器（D1，D2 --- Dn）将信号馈送到传输线，并且多个接收器（R1，R2 --- Rn）接收发送的信号。 多个AND门（A1，A2 --- An）接收来自接收器的输出，并且OR门（23）从AND门接收输出。 相应的异或门（31）连接到每对传输线，并且相应的滤波器（32）接收每个异或门的输出并驱动相应的与门。 因此，当传输线路24被中断时，执行中断的传输线路的检测，并且传输线路被切换，使得发送的信号不被中断。

公开(公告)号：EP0032957A1

公开(公告)日：1981-08-05

申请号：EP80901420.2

申请日：1980-07-29

申请人： FUJITSU LIMITED

发明人： TANIGUCHI, Shozo ,  SHINKE, Osamu ,  ISHII, Masami ,  KUBO, Shinichi

IPC分类号： G11C29/00 ,  G06F11/08 ,  G06F11/16

CPC分类号： G11C29/70 ,  F02P5/1506 ,  G06F11/1024 ,  G06F11/1044 ,  Y02T10/46

摘要： A data processing system for error processing and an error processing method, which system includes a main memory (M), an information processing unit (A), an error processing unit (EP) and an alternate memory. When an error arises in a portion of the main memory, corrected information is stored in the alternate memory. Then, under the control of the error processing unit (EP), the alternate memory is employed instead of the malfunctioning portion of the main memory. The alternate memory is adapted to be used only when the error is a fixed error or a burst error, in order to avoid a system shut-down caused by fixed- and soft-errors or burst- and soft-errors which occur during information processing. The alternate memory, therefore, is not used in a case where the error is a soft error. This imparts an additional advantage in that the size of the memory is reduced.

公开(公告)号：EP0032956A1

公开(公告)日：1981-08-05

申请号：EP80901416.0

申请日：1980-07-24

申请人： FUJITSU LIMITED

发明人： HATTORI, Akira ,  TSUCHIMOTO, Takamitsu

IPC分类号： G06F12/10 ,  G06F13/00

CPC分类号： G06F12/0607 ,  G06F12/0851 ,  G06F12/0864

摘要： The hierarchical memory consists of a group of buffer memories (12-1, 12-2, ...12-n) each of which is provided in each of plural central processing units (11-1, 11-2,...11-n), an intermediate buffer memory (13) and the main memory (14) having plural banks (23-0, 23-1, 23-2, 23-3). Both the intermediate buffer memory (13) and the main memory (14) are controlled by swap-control system and set-associative system. The two memories (13, 14) are accessed by address information containing a bank-selection-address-bit-group (42) and a set-selection-address-bit-group (43). The bank-selection-address-bit-group (42) is partially modified by a part of the set-selection-address-bit-group (43).