公开(公告)号：EP0822477B1

公开(公告)日：2003-09-24

申请号：EP97112808.7

申请日：1997-07-25

申请人： Hynix Semiconductor Inc.

发明人： Proebsting, Robert J.

IPC分类号： G05F3/20 ,  G11C5/14 ,  H03K17/06

CPC分类号： G05F3/205 ,  G11C5/146 ,  H02M3/073 ,  H02M2001/0032 ,  H02M2003/071 ,  H02M2003/075 ,  H03B5/04 ,  Y02B70/16

公开(公告)号：EP1221760A2

公开(公告)日：2002-07-10

申请号：EP01310959.0

申请日：2001-12-31

申请人： Nokia Corporation

发明人： Nurmi, Mikko

IPC分类号： H02M3/07

CPC分类号： H02M3/07 ,  H02M2003/071

摘要： A voltage combiner circuit is created with a first voltage source and a second voltage source a capacitor and a diode. The circuit employs two switches with one switch open while the other is closed thereby defining first and second half cycles of operation for the combiner circuit. The circuit employs a flying capacitor coupled in series with ground, a diode and a second voltage source to charge the capacitor to the level of the second voltage source during the first half cycle of operation. The circuit employs the second switch to couple the flying capacitor charged to the level of the second voltage source in series with the first voltage source creating a voltage level above a threshold voltage level required to turn the load ON.

摘要翻译： 电压合并器电路由第一电压源和第二电压源形成电容器和二极管。 该电路使用两个开关，其中一个开关断开而另一个闭合，从而为组合器电路定义第一和第二半操作周期。 该电路采用与地线串联的快速电容器，二极管和第二电压源在工作的前半个周期期间将电容器充电至第二电压源的电平。 该电路采用第二开关来将充电到第二电压源的电平的快速电容器与第一电压源串联，从而产生高于使负载接通所需的阈值电压电平的电压电平。

公开(公告)号：EP0880783B1

公开(公告)日：1999-10-13

申请号：EP96927429.9

申请日：1996-08-15

申请人： ADVANCED MICRO DEVICES INC.

发明人： CHANG, Chung, K. ,  CHEN, Johnny, C. ,  CLEVELAND, Lee, E.

IPC分类号： G11C16/06 ,  G11C5/14 ,  H02M3/07

CPC分类号： G11C16/30 ,  G11C5/145 ,  H02M3/073 ,  H02M2003/071 ,  H02M2003/075

摘要： A low supply voltage negative charge pump for generating a relatively high negative voltage to control gates of selected memory cells via wordlines in an array of flash EEPROM memory cells during flash erasure includes charge pump means (210) formed of a plurality of charge pump stages (201-206) and coupling capacitor means (C201-C212) for delivering clock signals to the plurality of charge pump stages. Each of the plurality of charge pump stages is formed of an N-channel intrinsic pass transistor (N1-N6), an N-channel intrinsic initialization transistor (MD1-MD6), and an N-channel intrinsic precharge transistor (MX3-MX7, MX1) which are disposed in separate p-wells so as to reduce body effect. As a result, the negative charge pump is operable using a supply voltage of +3 volts or lower.