摘要:
Disclosed is a fast Fourier transform circuit capable of high-speed reading and writing of data processed in the individual stages of a fast Fourier transform calculation without segmenting memory. The circuit is provided with: a calculation unit (1) which performs the fast Fourier calculations with digital Fourier transforms as structural elements; memory (2A, 2B) for storing the input/output data of the calculation unit (1); and a means (7) for controlling the writing of calculation results from the calculation unit (1) to the memory (2A, 2B) such that the order of reading data from the memory (2A, 2B) is the same at each stage in the multi-stage calculation performed on the data being processed by the calculation unit (11).
摘要:
An FFT algorithm that splits a large bit width waveform into two parts, making it possible to conduct the FFT with much lower logic resource consumption is disclosed. The waveform is split into its most significant bits and its least significant bits through division in the form of a bit shift. Each partial signal is then put through an FFT algorithm. The MSB FFT output is then right bit shifted. The two partial FFT's are summed to create a single output that is largely equivalent to an FFT of the original waveform. Rounding distortion is reduced by overlapping the MSB and LSB partial signals.
摘要:
In general, techniques are described that provide for 4x4 transforms for media coding. A number of different 4x4 transforms are described that adhere to these techniques. As one example, an apparatus includes a 4x4 discrete cosine transform (DCT) hardware unit. The DCT hardware unit implements an orthogonal 4x4 DCT having an odd portion that applies first and second internal factors (C, S) that are related to a scaled factor (?) such that the scaled factor equals a square root of a sum of a square of the first internal factor (C) plus a square of the second internal factor (S). The 4x4 DCT hardware unit applies the 4x4 DCT implementation to media data to transform the media data from a spatial domain to a frequency domain. As another example, an apparatus implements a non-orthogonal 4x4 DCT to improve coding gain.
摘要:
Embodiments of the present invention relate to a voice detector receiving an input signal that is divided into sub-signals that represent a frequency sub-band. The voice detector calculates, for each sub-band, a signal-to-noise (SNR) value based on a corresponding sub-signal for each sub-band and a background signal for each sub-band. The voice detector also calculates a power SNR value for each sub-band, where at least one of the power SNR values is calculated based on a non-linear function. The voice detector forms a single value based on the calculated power SNR values and compares the single value and a given threshold value to make a voice activity decision presented on an output port.
摘要:
An efficient lapped transform is realized using pre- and post-filters (or reversible overlap operators) that are structured of unit determinant component matrices. The pre-and post-filters are realized as a succession of planar rotational transforms and unit determinant planar scaling transforms. The planar scaling transforms can be implemented using planar shears or lifting steps. Further, the planar rotations and planar shears have an implementation as reversible/lossless operations, giving as a result, a reversible overlap operator.
摘要:
Estimates of spectral magnitude and phase are obtained by an estimation process using spectral information from analysis filter banks such as the Modified Discrete Cosine Transform. The estimation process may be implemented by convolution-like operations with impulse responses. Portions of the impulse responses may be selected for use in the convolution-like operations to trade off between computational complexity and estimation accuracy. Mathematical derivations of analytical expressions for filter structures and impulse responses are disclosed.
摘要:
The invention relates to a method for processing a signal, in particular a digital audio signal, suitable for being implemented by a digital signal processor (DSP) having libraries for calculating Fourier transforms from the complex number space to the complex number space, for digitally processing P input signals, P being an integer at least equal to 2, more particularly for filtering said P input signals by the convolution of sampled fast Fourier transforms (FFT), thus obtaining Q output signals, Q being an integer at least equal to 2. According to the invention, the method includes at least the following steps: - grouping said P input signals by twos, one representing the real portion and the other the imaginary portion of a complex number, thus defining one or more input vectors, - filtering said input vector or vectors, passing through the Fourier space, thus generating one or more output vectors, which are complex numbers, the real portion and the imaginary portion of said vector or each one of said output vectors respectively representing one of said Q output signals.