公开(公告)号：EP2862062A4

公开(公告)日：2016-12-28

申请号：EP13804852

申请日：2013-06-11

Applicant: SOFT MACHINES INC

Inventor： ABDALLAH MOHAMMAD

IPC: G06F9/38

CPC classification number: G06F9/3836 ,  G06F5/14 ,  G06F9/30043 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/3851 ,  G06F9/3855 ,  G06F2205/063 ,  G06F2205/064

Abstract: An out of order processor. The processor includes a distributed load queue and a distributed store queue that maintain single program sequential semantics while allowing an out of order dispatch of loads and stores across a plurality of cores and memory fragments; wherein the processor allocates other instructions besides loads and stores beyond the actual physical size limitation of the load/store queue; and wherein the other instructions can be dispatched and executed even though intervening loads or stores do not have spaces in the load store queue.

Abstract translation: 一个乱序处理器。 处理器包括分布式负载队列和分布式存储队列，其维护单个程序顺序语义，同时允许跨多个核心和存储器片段的负载和存储的乱序分派; 其中所述处理器除了加载和存储之外分配超出所述加载/存储队列的实际物理大小限制的其他指令; 并且其中即使中间加载或存储在加载存储队列中没有空格，也可以调度和执行其他指令。

公开(公告)号：EP2616928B1

公开(公告)日：2016-11-02

申请号：EP11826042.1

申请日：2011-09-16

Applicant: Soft Machines, Inc.

Inventor： ABDALLAH, Mohammad

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3806 ,  G06F9/30018 ,  G06F9/30029 ,  G06F9/30047 ,  G06F9/3804 ,  G06F9/3836 ,  G06F9/3844 ,  G06F9/3869 ,  G06F12/0875 ,  G06F2212/1016 ,  G06F2212/452

Abstract: A method of identifying instructions including accessing a plurality of instructions that comprise multiple branch instructions. For each branch instruction of the multiple branch instructions, a respective first mask is generated representing instructions that are executed if a branch is taken. A respective second mask is generated representing instructions that are executed if the branch is not taken. A prediction output is received that comprises a respective branch prediction for each branch instruction. For each branch instruction, the prediction output is used to select a respective resultant mask from among the respective first and second masks. For each branch instruction, a resultant mask of a subsequent branch is invalidated if a previous branch is predicted to branch over said subsequent branch. A logical operation is performed on all resultant masks to produce a final mask. The final mask is used to select a subset of instructions for execution.

公开(公告)号：EP2783280A4

公开(公告)日：2016-07-20

申请号：EP11876128

申请日：2011-11-22

Applicant: SOFT MACHINES INC

Inventor： ABDALLAH MOHAMMAD

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3802 ,  G06F9/3017 ,  G06F9/3808 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3853 ,  G06F9/3887

Abstract: A method for accelerating code optimization a microprocessor. The method includes fetching an incoming microinstruction sequence using an instruction fetch component and transferring the fetched macroinstructions to a decoding component for decoding into microinstructions. Optimization processing is performed by reordering the microinstruction sequence into an optimized microinstruction sequence comprising a plurality of dependent code groups. The plurality of dependent code groups are then output to a plurality of engines of the microprocessor for execution in parallel. A copy of the optimized microinstruction sequence is stored into a sequence cache for subsequent use upon a subsequent hit optimized microinstruction sequence.

公开(公告)号：EP2710481A4

公开(公告)日：2016-03-30

申请号：EP12789667

申请日：2012-05-18

Applicant: SOFT MACHINES INC

Inventor： ABDALLAH MOHAMMAD

IPC: G06F13/14 ,  G06F9/06 ,  G06F9/38 ,  G06F9/50 ,  G06F13/36 ,  G06F13/38

CPC classification number: G06F9/3005 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3851 ,  G06F9/3885 ,  G06F9/3891 ,  G06F9/5005 ,  G06F13/1673 ,  G06F13/1689 ,  G06F13/4068

Abstract: A method for decentralized resource allocation in an integrated circuit. The method includes receiving a plurality of requests from a plurality of resource consumers of a plurality of partitionable engines to access a plurality resources, wherein the resources are spread across the plurality of engines and are accessed via a global interconnect structure. At each resource, a number of requests for access to said each resource are added. At said each resource, the number of requests are compared against a threshold limiter. At said each resource, a subsequent request that is received that exceeds the threshold limiter is canceled. Subsequently, requests that are not canceled within a current clock cycle are implemented.

Abstract translation: 一种用于在集成电路中的共享互连结构的分配方法被游离缺失盘。 该方法包括接收从资源消费者发动机的多个的多个请求的多元性访问资源，worin的资源在发动机的多个扩展的多个部分并加以包含数据用于支持多个代码序列的执行。 因此，该方法包括争夺资源的雅舞蹈多个具有从资源消费者的多个请求。 最后，该方法包括经由全局互连结构访问资源的多元性，worin全球互连结构具有总线的一个有限数量的可访问的每个时钟周期，并且worin全球互连结构包括共享互连结构的复数，worin每个共享互连 结构是由每个发射器和每个接收器的共享。

公开(公告)号：EP2972912A1

公开(公告)日：2016-01-20

申请号：EP14768040.9

申请日：2014-03-13

Applicant: Soft Machines, Inc.

Inventor： ABDALLAH, Mohammad

IPC: G06F13/14 ,  G06F13/38

CPC classification number: G06F9/3885 ,  G06F9/3004 ,  G06F9/3853 ,  G06F9/462 ,  G06F12/00 ,  G06F12/0853 ,  G06F12/0886 ,  G06F13/00 ,  G06F15/17318 ,  G06F2212/1041 ,  G06F2212/1056 ,  H04L12/28 ,  H04L49/1523

Abstract: A method for line speed interconnect processing. The method includes receiving initial inputs from an input communications path, performing a pre-sorting of the initial inputs by using a first stage interconnect parallel processor to create intermediate inputs, and performing the final combining and splitting of the intermediate inputs by using a second stage interconnect parallel processor to create resulting outputs. The method further includes transmitting the resulting outputs out of the second stage at line speed.

Abstract translation: 一种线速互连处理方法。 该方法包括从输入通信路径接收初始输入，通过使用第一级互连并行处理器来执行初始输入的预先分类以创建中间输入，并且通过使用第二级来执行中间输入的最终组合和分割 互连并行处理器以创建结果输出。 该方法还包括以线速度将结果输出传送出第二级。

公开(公告)号：EP2972845A1

公开(公告)日：2016-01-20

申请号：EP14769450.9

申请日：2014-03-12

Applicant: Soft Machines, Inc.

Inventor： ABDALLAH, Mohammad

IPC: G06F9/46

CPC classification number: G06F9/4881 ,  G06F9/30094 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3851 ,  G06F9/48 ,  G06F9/4887 ,  G06F9/50 ,  G06F9/5005 ,  G06F9/5011 ,  G06F9/5016 ,  G06F9/5027 ,  G06F9/5038 ,  G06F9/52 ,  G06F9/524

Abstract: A method for executing multithreaded instructions grouped into blocks. The method includes receiving an incoming instruction sequence using a global front end; grouping the instructions to form instruction blocks, wherein the instructions of the instruction blocks are interleaved with multiple threads; scheduling the instructions of the instruction block to execute in accordance with the multiple threads; and tracking execution of the multiple threads to enforce fairness in an execution pipeline.

Abstract translation: 一种用于执行分组为块多线程指令的方法。 该方法包括使用一个全局前端在传入指令序列接收; 分组的指令，以形成指令块，worin的指令块的指令，以与多个线程进行交织; 调度指令块与所述多个线程雅舞蹈执行的指令; 和跟踪多个线程的执行强制公平管道的执行。

公开(公告)号：EP2862084A1

公开(公告)日：2015-04-22

申请号：EP13803753.6

申请日：2013-06-13

Applicant: Soft Machines, Inc.

Inventor： ABDALLAH, Mohammad

IPC: G06F12/00

CPC classification number: G06F9/528 ,  G06F9/30043 ,  G06F9/30145 ,  G06F9/3017 ,  G06F9/30185 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/3834 ,  G06F9/3855 ,  G06F12/0831

Abstract: A method for forwarding data from the store instructions to a corresponding load instruction in an out of order processor. The method includes accessing an incoming sequence of instructions; reordering the instructions in accordance with processor resources for dispatch and execution; ensuring a closest earlier store in machine order for to a corresponding load, by determining if said store has an actual age but said corresponding load does not have an actual age, then said store is earlier than said corresponding load; if said corresponding load has an actual age but said store does not have an actual age, then said corresponding load is earlier than said store; if neither said corresponding load or said store have an actual age, then a virtual identifier table is used to determine which is earlier; and if both said corresponding load and said store have actual ages, then the actual ages are used to determine which is earlier.

Abstract translation: 一种用于在乱序处理器从存储指令转发数据到对应的加载指令的方法。 该方法包括访问到的指令输入序列; 重排与分派和执行处理器资源在雅舞蹈的说明; 确保以便机器最近早些时候存储到相应的负载，以确定开采，如果上述商店具有实际年龄，但表示相应的负载不必实际年龄，然后说店是比所述相应的负载早些时候; 说，如果相应的负载有实际年龄，但表示店内没有实际年龄那么相应的所述负载早于上述商店; 如果既不所述相应的加载或存储。所述得的实际年龄，然后虚拟标识符表被用于确定哪个是早些时候; 如果双方都表示相应的加载和存储有说实际年龄，则实际年龄来确定性矿所有这一切早。

公开(公告)号：EP2689327A4

公开(公告)日：2014-08-13

申请号：EP12764627

申请日：2012-03-23

Applicant: SOFT MACHINES INC

Inventor： ABDALLAH MOHAMMAD

IPC: G06F9/06 ,  G06F9/30 ,  G06F12/08 ,  G06F15/76

CPC classification number: G06F9/3009 ,  G06F9/30105 ,  G06F9/30123 ,  G06F9/34 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3851 ,  G06F9/5038 ,  G06F9/5077 ,  G06F2209/506 ,  Y02B60/142 ,  Y02B60/167 ,  Y02D10/22 ,  Y02D10/36

Abstract: A method for executing instructions using a plurality of virtual cores for a processor. The method includes receiving an incoming instruction sequence using a global front end scheduler, and partitioning the incoming instruction sequence into a plurality of code blocks of instructions. The method further includes generating a plurality of inheritance vectors describing interdependencies between instructions of the code blocks, and allocating the code blocks to a plurality of virtual cores of the processor, wherein each virtual core comprises a respective subset of resources of a plurality of partitionable engines. The code blocks are executed by using the partitionable engines in accordance with a virtual core mode and in accordance with the respective inheritance vectors.

Abstract translation: 一种用于使用用于处理器的多个虚拟核来执行指令的方法。 该方法包括使用全局前端调度器接收输入指令序列，并将输入指令序列划分成多个指令代码块。 该方法还包括生成描述代码块的指令之间的相互依赖性的多个继承向量，以及将代码块分配给处理器的多个虚拟核心，其中每个虚拟核心包括多个可分区引擎的相应资源子集 。 根据虚拟核心模式并根据相应的继承向量，通过使用可分区引擎执行代码块。

公开(公告)号：EP2710481A2

公开(公告)日：2014-03-26

申请号：EP12789667.8

申请日：2012-05-18

Applicant: Soft Machines, Inc.

Inventor： ABDALLAH, Mohammad

IPC: G06F13/14 ,  G06F13/38 ,  G06F9/06

CPC classification number: G06F9/3005 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3851 ,  G06F9/3885 ,  G06F9/3891 ,  G06F9/5005 ,  G06F13/1673 ,  G06F13/1689 ,  G06F13/4068

Abstract: A method for decentralized resource allocation in an integrated circuit. The method includes receiving a plurality of requests from a plurality of resource consumers of a plurality of partitionable engines to access a plurality resources, wherein the resources are spread across the plurality of engines and are accessed via a global interconnect structure. At each resource, a number of requests for access to said each resource are added. At said each resource, the number of requests are compared against a threshold limiter. At said each resource, a subsequent request that is received that exceeds the threshold limiter is canceled. Subsequently, requests that are not canceled within a current clock cycle are implemented.

公开(公告)号：EP2710480A1

公开(公告)日：2014-03-26

申请号：EP12788989.7

申请日：2012-05-18

Applicant: Soft Machines, Inc.

Inventor： ABDALLAH, Mohammad

IPC: G06F13/14 ,  G06F13/38 ,  G06F9/06

CPC classification number: G06F9/5077 ,  G06F9/3012 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3851 ,  G06F9/3891 ,  G06F9/46 ,  G06F9/4881 ,  G06F9/52 ,  G06F13/4068 ,  G06F15/80

Abstract: A global interconnect system. The global interconnect system includes a plurality of resources having data for supporting the execution of multiple code sequences and a plurality of engines for implementing the execution of the multiple code sequences. A plurality of resource consumers are within each of the plurality of engines. A global interconnect structure is coupled to the plurality of resource consumers and coupled to the plurality of resources to enable data access and execution of the multiple code sequences, wherein the resource consumers access the resources through a per cycle utilization of the global interconnect structure.