公开(公告)号：EP2836941A1

公开(公告)日：2015-02-18

申请号：EP12849946.4

申请日：2012-11-07

Applicant: Global Supercomputing Corporation

Inventor： EBCIOGLU, Kemal ,  KULTURSAY, Emre ,  KANDEMIR, Mahmut Taylan

IPC: G06F17/50 ,  G06F9/24

Abstract: The invention comprises (i) a compilation method for automatically converting a single-threaded software program into an application-specific supercomputer, and (ii) the supercomputer system structure generated as a result of applying this method. The compilation method comprises: (a) Converting an arbitrary code fragment from the application into customized hardware whose execution is functionally equivalent to the software execution of the code fragment; and (b) Generating interfaces on the hardware and software parts of the application, which (i) Perform a software-to-hardware program state transfer at the entries of the code fragment; (ii) Perform a hardware-to-software program state transfer at the exits of the code fragment; and (iii) Maintain memory coherence between the software and hardware memories. If the resulting hardware design is large, it is divided into partitions such that each partition can fit into a single chip. Then, a single union chip is created which can realize any of the partitions.

公开(公告)号：EP2836941B1

公开(公告)日：2020-09-02

申请号：EP12849946.4

申请日：2012-11-07

Applicant: Global Supercomputing Corporation

Inventor： EBCIOGLU, Kemal ,  KULTURSAY, Emre ,  KANDEMIR, Mahmut Taylan

IPC: G06F30/327 ,  G06F30/30 ,  G06F8/41 ,  G06F15/173 ,  G06F115/10

公开(公告)号：EP2839372A1

公开(公告)日：2015-02-25

申请号：EP12867516.2

申请日：2012-12-29

Applicant: Global Supercomputing Corporation

Inventor： EBCIOGLU, Kemal ,  DOGAN, Atakan ,  ALTUG, Reha Oguz ,  LIPASTI, Mikko Herman ,  OZKURAL, Eray

IPC: G06F9/50

CPC classification number: G06F9/45533 ,  G06F9/45558 ,  G06F9/5077 ,  G06F15/7871 ,  G06F2009/4557 ,  Y02D10/12 ,  Y02D10/13 ,  Y02D10/26 ,  Y02D10/28

Abstract: A parallel hypervisor system for virtualizing application-specific supercomputers is disclosed. The hypervisor system comprises (a) at least one software-virtual hardware pair consisting of a software application, and an application-specific virtual supercomputer for accelerating the said software application, wherein (i) The virtual supercomputer contains one or more virtual tiles; and (ii) The software application and the virtual tiles communicate among themselves with messages; (b) One or more reconfigurable physical tiles, wherein each virtual tile of each supercomputer can be implemented on at least one physical tile, by configuring the physical tile to perform the virtual tile's function; and (c) A scheduler implemented substantially in hardware, for parallel pre-emptive scheduling of the virtual tiles on the physical tiles.