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1.发明公开Method and apparatus for prioritizing and handling errors in a computer system 失效在计算机系统中优先和处理错误的方法和装置公开(公告)号：EP0730230A2
公开(公告)日：1996-09-04
申请号：EP96103124.2
申请日：1996-03-01
Applicant: HAL COMPUTER SYSTEMS, INC.
Inventor： Chang, Chih-Wei David , Boney, Joel Frederick , Kohli, Jaspal
CPC classification number: G06F11/073 , G06F11/0793
Abstract: A computer system (10) includes a central processing unit (12) and a memory management unit (18) having a plurality of functional units, such as a memory interface unit, a remote interface unit (60), a cache interface unit (70), and a translation unit (50). Each functional unit has a low priority error queue for storing error information for errors having a low priority. Some functional units also have a high priority error queue for storing error information for errors having a high priority error. Based on the status of the error queues, the memory management unit prioritizes and handles errors caused by hardware failures. For low priority errors, an interrupt request signal is sent to the central processing unit (122). For high priority errors, a RED ALERT signal is sent to the processing unit (112) to cause the processing unit to give immediate attention to the error. For high priority error queue overflows, a failure signal is generated (102) which causes the system to be halted and the contents of the system to be scanned out (104). Thus, errors are prioritized and handled accordingly.
Abstract translation: 一种计算机系统（10）包括中央处理单元（12），并具有的功能单元的多个存储器管理单元（18），检查作为存储接口单元，远程接口单元（60），高速缓存接口单元（70 ），和一个翻译单元（50）。 每个功能单元具有用于存储对于具有低优先级的错误的错误信息的低优先级的错误队列。 因此，一些功能单元具有用于存储用于具有高优先级的错误的错误的错误信息高优先级错误队列。 基于错误队列的状态时，内存管理单元和优先处理由硬件故障导致的错误。 对于低优先级的错误中断请求信号被发送到中央处理单元（122）。 对于高优先级的错误，红色警报信号被发送到所述处理单元（112），以使处理单元给予立即注意到该错误。 对于高优先级的错误队列溢出时，会产生故障信号（102），从而导致系统被暂停，并且系统中的内容将被扫描出（104）。 因此，错误的优先级和相应的处理。
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2.发明公开Method and apparatus for prioritizing and handling errors in a computer system 失效在计算机系统中优先和处理错误的方法和装置
公开(公告)号：EP0730230A3
公开(公告)日：1999-12-22
申请号：EP96103124.2
申请日：1996-03-01
Applicant: HAL COMPUTER SYSTEMS, INC.
Inventor： Chang, Chih-Wei David , Boney, Joel Frederick , Kohli, Jaspal
CPC classification number: G06F11/073 , G06F11/0793
Abstract: A computer system (10) includes a central processing unit (12) and a memory management unit (18) having a plurality of functional units, such as a memory interface unit, a remote interface unit (60), a cache interface unit (70), and a translation unit (50). Each functional unit has a low priority error queue for storing error information for errors having a low priority. Some functional units also have a high priority error queue for storing error information for errors having a high priority error. Based on the status of the error queues, the memory management unit prioritizes and handles errors caused by hardware failures. For low priority errors, an interrupt request signal is sent to the central processing unit (122). For high priority errors, a RED ALERT signal is sent to the processing unit (112) to cause the processing unit to give immediate attention to the error. For high priority error queue overflows, a failure signal is generated (102) which causes the system to be halted and the contents of the system to be scanned out (104). Thus, errors are prioritized and handled accordingly.
