公开(公告)号：EP1556908A2

公开(公告)日：2005-07-27

申请号：EP03776825.6

申请日：2003-10-30

Applicant: Infineon Technologies AG

Inventor： GRAHAM, Andrew ,  HOFMANN, Franz ,  HÖNLEIN, Wolfgang ,  KRETZ, Johannes ,  KREUPL, Franz ,  LANDGRAF, Erhard ,  LUYKEN, Richard, Johannes ,  RÖSNER, Wolfgang ,  SCHULZ, Thomas ,  SPECHT, Michael

IPC: H01L51/20

CPC classification number: G11C13/025 ,  B82Y10/00 ,  G11C2213/17 ,  H01L27/283 ,  H01L51/0048 ,  H01L51/0052 ,  H01L51/0512

Abstract: The invention relates to a field effect transistor assembly and an integrated circuit array. The field effect transistor assembly contains a substrate, a first wiring plane with a first source/drain region on the substrate and a second wiring plane with a second source/drain region above the first wiring plane. The field effect transistor assembly also comprises at least one vertical nanoelement as a channel region, which is situated between and coupled to both wiring planes. The nanoelement is at least partially surrounded by electrically conductive material, forming a gate region, whereby electrically insulating material is provided between the nanoelement and the electrically conductive material to act as a gate insulating layer.

公开(公告)号：EP1535345A1

公开(公告)日：2005-06-01

申请号：EP03747922.7

申请日：2003-08-21

Applicant: Infineon Technologies AG

Inventor： HOFMANN, Franz ,  LANDGRAF, Erhard ,  LUYKEN, Richard, Johannes ,  SCHULZ, Thomas ,  SPECHT, Michael

IPC: H01L29/792 ,  H01L27/115

CPC classification number: H01L21/28282 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7923 ,  H01L29/7926

Abstract: The invention relates to a semiconductor memory with a number of memory cells, whereby each memory cell comprises a semiconductor layer (p-well), arranged on a substrate (p-sub), the semiconductor surface of which comprises a stage between a deeper (10) and a shallower (12) semiconductor region, viewed in the substrate normal direction, at least one conducting doped deeper contact region (22, 24), embodied in the deeper semiconductor region (10),a conducting doped shallower contact region (20), embodied in the shallower semiconductor region (12), at least one channel region, running in the semiconductor layer (p-well) between the deeper (22, 24) and the shallower contact region (20), at least one electrically-insulating trapping layer (28), for the trapping and releasing of charge carriers arranged on a gate oxide layer (26) adjacent to the channel region and at least one gate electrode (32) for control of the electrical conductivity of the channel region, whereby the gate electrode (32) is partly adjacent to a control oxide layer (30) arranged on the trapping layer (28) and partly adjacent to the gate oxide layer (26) arranged on the channel region.

公开(公告)号：EP1535335B1

公开(公告)日：2008-07-09

申请号：EP03793746.3

申请日：2003-08-21

Applicant: Infineon Technologies AG

Inventor： HOFMANN, Franz ,  LANDGRAF, Erhard ,  LUYKEN, Richard, Johannes ,  SCHULZ, Thomas ,  SPECHT, Michael

IPC: H01L27/115 ,  H01L21/8246 ,  H01L29/792 ,  H01L21/28 ,  H01L21/336

CPC classification number: H01L29/7926 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7923

Abstract: The invention relates to a semiconductor memory with a number of memory cells, whereby each of the memory cells comprises four vertical memory transistors with trapping layers. The shallower contact regions are embodied in a semiconductor region running at an angle to the lines and gaps of the cell field, whereby the gate electrode preferably runs on the stage lateral surfaces of the shallower semiconductor region. A memory density of 1-2F2 per bit may thus be achieved.

公开(公告)号：EP1556909A1

公开(公告)日：2005-07-27

申请号：EP03778239.8

申请日：2003-10-29

Applicant: Infineon Technologies AG

Inventor： GRAHAM, Andrew ,  HOFMANN, Franz ,  HÖNLEIN, Wolfgang ,  KRETZ, Johannes ,  KREUPL, Franz ,  LANDGRAF, Erhard ,  LUYKEN, Richard, Johannes ,  RÖSNER, Wolfgang ,  SCHULZ, Thomas ,  SPECHT, Michael

IPC: H01L51/20 ,  H01L51/30 ,  H01L29/786 ,  H01L21/335 ,  H01L29/775

CPC classification number: H01L29/78642 ,  B82Y10/00 ,  H01L27/283 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/66787 ,  H01L29/775 ,  H01L51/0048 ,  H01L51/0052 ,  H01L51/0512

Abstract: The invention relates to a vertical integrated component, a component arrangement and a method for production of a vertical integrated component. The vertical integrated component has a first electrical conducting layer (101), a mid layer (102), partly embodied from dielectric material on the first electrical conducting layer, a second electrical conducting layer (103) on the mid layer and a nanostructure (104) integrated in a through hole introduced in the mid layer with a first end section coupled to the first electrical conducting layer and a second end section coupled to the second electrical conducting layer. The mid layer comprises a third electrical conducting layer (105) between two adjacent dielectric partial layers (102a, 102b) the thickness of which is less than the thickness of at least one of the dielectric partial layers.

公开(公告)号：EP1741141A1

公开(公告)日：2007-01-10

申请号：EP05748159.0

申请日：2005-04-22

Applicant: Infineon Technologies AG

Inventor： HOFMANN, Franz ,  LANDGRAF, Erhard ,  LUYKEN, Richard, Johannes

IPC: H01L29/786 ,  H01L27/12 ,  H01L21/84

CPC classification number: H01L21/845 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78636

Abstract: The invention relates to a fin field effect transistor arrangement comprising a substrate, a first fin field effect transistor on and/or in said substrate that has a fin in which the channel region is formed between the first and second source/drain region, and above which the gate region is formed, and comprising a second fin field effect transistor on and/or in the substrate that has a fin in which the channel region is formed between the first and second source/drain region, and above which the gate region is formed. The height of the fin of the first fin field effect transistor arrangement is greater than the height of the fin of the second fin field effect transistor.

公开(公告)号：EP1535335A2

公开(公告)日：2005-06-01

申请号：EP03793746.3

申请日：2003-08-21

Applicant: Infineon Technologies AG

Inventor： HOFMANN, Franz ,  LANDGRAF, Erhard ,  LUYKEN, Richard, Johannes ,  SCHULZ, Thomas ,  SPECHT, Michael

IPC: H01L27/115 ,  H01L21/8246 ,  H01L29/792 ,  H01L21/28 ,  H01L21/336

CPC classification number: H01L29/7926 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7923

Abstract: The invention relates to a semiconductor memory with a number of memory cells, whereby each of the memory cells comprises four vertical memory transistors with trapping layers. The shallower contact regions are embodied in a semiconductor region running at an angle to the lines and gaps of the cell field, whereby the gate electrode preferably runs on the stage lateral surfaces of the shallower semiconductor region. A memory density of 1-2F2 per bit may thus be achieved.

公开(公告)号：EP1568087A1

公开(公告)日：2005-08-31

申请号：EP03778240.6

申请日：2003-10-29

Applicant: Infineon Technologies AG

Inventor： GRAHAM, Andrew ,  HOFMANN, Franz ,  HÖNLEIN, Wolfgang ,  KRETZ, Johannes ,  KREUPL, Franz ,  LANDGRAF, Erhard ,  LUYKEN, Richard, Johannes ,  RÖSNER, Wolfgang ,  SCHULZ, Thomas ,  SPECHT, Michael

IPC: H01L51/20

CPC classification number: H01L29/7888 ,  B82Y10/00 ,  G11C13/025 ,  G11C2213/17 ,  H01L21/28282 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/1203 ,  H01L27/28 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926 ,  H01L51/0048 ,  H01L51/0052 ,  H01L51/057

Abstract: The invention relates to a non-volatile memory cell, memory cell arrangement and method for production of a non-volatile memory cell. The non-volatile memory cell comprises a vertical field-effect transistor, with a nanoelement arranged as channel region and an electrical insulating layer at least partly surrounding the nanoelement as charge storage layer and as gate-insulating layer. The above is arranged such that electric charge carriers may be selectively introduced into or removed from the above and the electrical conductivity characteristics of the nanoelement may be influenced by the electrical charge carriers introduced into electrical insulating layer.

公开(公告)号：EP1556893A2

公开(公告)日：2005-07-27

申请号：EP03778241.4

申请日：2003-10-29

Applicant: Infineon Technologies AG

Inventor： GRAHAM, Andrew ,  HOFMANN, Franz ,  HÖNLEIN, Wolfgang ,  KRETZ, Johannes ,  KREUPL, Franz ,  LANDGRAF, Erhard ,  LUYKEN, Richard, Johannes ,  RÖSNER, Wolfgang ,  SCHULZ, Thomas ,  SPECHT, Michael

IPC: H01L21/8239

CPC classification number: G11C13/025 ,  B82Y10/00 ,  G11C13/0033 ,  G11C2213/16 ,  H01L27/10841 ,  H01L27/10864 ,  H01L27/10876 ,  H01L27/283 ,  H01L51/0048 ,  H01L51/0052 ,  H01L51/0512 ,  H01L51/057

Abstract: The invention relates to a memory cell, memory cell arrangement, structuring arrangement and method for production of a memory cell. The memory cell has a vertical gate transistor and a memory capacitor, whereby the vertical gate transistor comprises a semiconducting nanostructure, grown on at least part of the memory capacitor.

公开(公告)号：EP1535336A2

公开(公告)日：2005-06-01

申请号：EP03793747.1

申请日：2003-08-21

Applicant: Infineon Technologies AG

Inventor： HOFMANN, Franz ,  LANDGRAF, Erhard ,  LUYKEN, Richard, Johannes ,  RÖSNER, Wolfgang ,  SPECHT, Michael

IPC: H01L27/115

CPC classification number: H01L21/28273 ,  G11C16/0466 ,  H01L21/28282 ,  H01L21/845 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/785 ,  H01L29/7881 ,  H01L29/792 ,  Y10S257/903 ,  Y10S257/904 ,  Y10S257/905

Abstract: The invention relates to a semiconductor memory comprising a plurality of memory cells, each memory cell comprising the following: a first conductively doped contact area (S/D), a second conductively doped contact area (S/D) and a channel region arranged therebetween, which are embodied in a plate-type rib (FIN) made of a semiconductor material and which are arranged successively in the above-mentioned order in the longitudinal direction of the rib (FIN), a memory layer (18) which is embodied in order to program the memory cell and which is arranged on the upper rib side (10) and distanced by means a first insulating layer (20), said memory layer (18) protruding over at least one (12) of the lateral rib surfaces (12) in a normal direction of one lateral rib surface (12), such that said one lateral rib surface (12) and the upper rib surface (10) form an injection edge (16) for injecting charge carriers from the channel region into the memory layer (18); and at least one gate electrode (WL1).

公开(公告)号：EP1472722A2

公开(公告)日：2004-11-03

申请号：EP03737237.2

申请日：2003-01-23

Applicant: Infineon Technologies AG

Inventor： HOFMANN, Franz ,  LANDGRAF, Erhard ,  LUYKEN, Hannes

IPC: H01L21/28 ,  H01L29/792 ,  H01L21/8246 ,  H01L27/115

CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/66833 ,  H01L29/792

Abstract: The invention relates to NROM memory cells that are disposed in trenches that are etched into the semiconductor material. The memory layer composed of a nitride layer (3) that is interposed between two oxide layers (2, 4) is applied to the trench walls before the dopants for source and drain (7) are implanted. The implantation regions of source and drain are thus prevented from being damaged by the high temperature loads of the component during production of the memory layer as the respective dopant is introduced only later on. Polysilicon gate electrodes (5) are connected to word lines (11).

Abstract translation: 本发明涉及设置在蚀刻到半导体材料中的沟槽中的NROM存储器单元。 在注入用于源极和漏极（7）的掺杂剂之前，将由介于两个氧化物层（2,4）之间的氮化物层（3）构成的存储层施加到沟槽壁。 因此在制造存储层期间防止源极和漏极的注入区域被组件的高温负载损坏，因为相应的掺杂剂仅在稍后被引入。 多晶硅栅电极（5）连接到字线（11）。