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公开(公告)号：EP1702269B1
公开(公告)日：2013-09-04
申请号：EP04815427.2
申请日：2004-12-24
Applicant: Intel Corporation
Inventor： SUBRAMONEY, Sreevinas , HUDSON, Richard , SERRANO, Mauricio , ADL-TABATABAI, Ali-Reza
CPC classification number: G06F11/348 , G06F12/0253 , G06F12/0269 , G06F2201/88 , G06F2201/885 , Y10S707/99957
Abstract: Techniques are described for optimizing memory management in a processor system. The techniques may be implemented on processors that include on-chip performance monitoring and on systems where an external performance monitor is coupled to a processor. Processors that include a Performance Monitoring Unit (PMU) are examples. The PMU may store data on read and write cache misses, as well as data on translation lookaside buffer (TLB) misses. The data from the PMU is used to determine if any memory regions within a memory heap are delinquent memory regions, i.e., regions exhibiting high numbers of memory problems or stalls. If delinquent memory regions are found, the memory manager, such as a garbage collection routine, can efficiently optimize memory performance as well as the mutators performance by improving the layout of objects in the heap. In this way, memory management routines may be focused based on dynamic and real-time memory performance data.
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2.发明公开METHODS AND APPARATUS TO DYNAMICALLY INSERT PREFETCH INSTRUCTIONS BASED ON GARBAGE COLLECTOR ANALYSIS AND LAYOUT OF OBJECTS 有权方法及装置动态插入初步答案说明，垃圾收集分析和布局对象的BASIS
公开(公告)号：EP1695212A1
公开(公告)日：2006-08-30
申请号：EP04812905.0
申请日：2004-12-03
Applicant: Intel Corporation
Inventor： SUBRAMONEY, Sreenivas , SERRANO, Mauricio , HUDSON, Richard , ADL-TABATABAI, Ali-Reza
CPC classification number: G06F12/0253 , G06F12/0862 , G06F2212/6026
Abstract: Methods and apparatus to dynamically insert prefetch instructions are disclosed. In an example method, one or more samples associated with cache misses are identified from a performance monitoring unit in a processor system. Based on sample information associated with the one or more samples, delinquent information is generated. To dynamically insert one or more prefetch instructions, a prefetch point is identified based on the delinquent information.
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3.发明授权METHODS AND APPARATUS TO DYNAMICALLY INSERT PREFETCH INSTRUCTIONS BASED ON GARBAGE COLLECTOR ANALYSIS AND LAYOUT OF OBJECTS 有权方法及装置动态插入初步答案说明，垃圾收集分析和布局对象的BASIS
公开(公告)号：EP1695212B1
公开(公告)日：2009-04-15
申请号：EP04812905.0
申请日：2004-12-03
Applicant: Intel Corporation
Inventor： SUBRAMONEY, Sreenivas , SERRANO, Mauricio , HUDSON, Richard , ADL-TABATABAI, Ali-Reza
CPC classification number: G06F12/0253 , G06F12/0862 , G06F2212/6026
Abstract: Methods and apparatus to dynamically insert prefetch instructions are disclosed. In an example method, one or more samples associated with cache misses are identified from a performance monitoring unit in a processor system. Based on sample information associated with the one or more samples, delinquent information is generated. To dynamically insert one or more prefetch instructions, a prefetch point is identified based on the delinquent information.
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4.发明授权METHODS AND APPARATUS TO DYNAMICALLY INSERT PREFETCH INSTRUCTIONS BASED ON COMPILER AND GARBAGE COLLECTOR ANALYSIS 有权用于动态插入初步答案说明，编译器的基础，方法和设备的垃圾收集分析
公开(公告)号：EP1695213B1
公开(公告)日：2008-10-01
申请号：EP04813423.3
申请日：2004-12-08
Applicant: Intel Corporation
Inventor： SERRANO, Mauricio , SUBRAMONEY, Sreenivas , HUDSON, Richard , ADL-TABATABAI, Ali-Reza
CPC classification number: G06F12/0253
Abstract: Methods and apparatus to insert prefetch instructions based on garbage collector analysis and compiler analysis are disclosed. In an example method, one or more batches of samples associated with cache misses from a performance monitoring unit in a processor system are received. One or more samples from the one or more batches of samples based on delinquent information are selected. A performance impact indicator associated with the one or more samples is generated. Based on the performance indicator, at least one of a garbage collector analysis and a compiler analysis is initiated to identify one or more delinquent paths. Based on the at least one of the garbage collector analysis and the compiler analysis, one or more prefetch points to insert prefetch instructions are identified.
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公开(公告)号：EP1702269A1
公开(公告)日：2006-09-20
申请号：EP04815427.2
申请日：2004-12-24
Applicant: Intel Corporation
Inventor： SUBRAMONEY, Sreevinas , HUDSON, Richard , SERRANO, Mauricio , ADL-TABATABAI, Ali-Reza
CPC classification number: G06F11/348 , G06F12/0253 , G06F12/0269 , G06F2201/88 , G06F2201/885 , Y10S707/99957
Abstract: Techniques are described for optimizing memory management in a processor system. The techniques may be implemented on processors that include on-chip performance monitoring and on systems where an external performance monitor is coupled to a processor. Processors that include a Performance Monitoring Unit (PMU) are examples. The PMU may store data on read and write cache misses, as well as data on translation lookaside buffer (TLB) misses. The data from the PMU is used to determine if any memory regions within a memory heap are delinquent memory regions, i.e., regions exhibiting high numbers of memory problems or stalls. If delinquent memory regions are found, the memory manager, such as a garbage collection routine, can efficiently optimize memory performance as well as the mutators performance by improving the layout of objects in the heap. In this way, memory management routines may be focused based on dynamic and real-time memory performance data.
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6.发明公开METHODS AND APPARATUS TO DYNAMICALLY INSERT PREFETCH INSTRUCTIONS BASED ON COMPILER AND GARBAGE COLLECTOR ANALYSIS 有权用于动态插入初步答案说明，编译器的基础，方法和设备的垃圾收集分析
公开(公告)号：EP1695213A1
公开(公告)日：2006-08-30
申请号：EP04813423.3
申请日：2004-12-08
Applicant: INTEL CORPORATION
Inventor： SERRANO, Mauricio , SUBRAMONEY, Sreenivas , HUDSON, Richard , ADL-TABATABAI, Ali-Reza
CPC classification number: G06F12/0253
Abstract: Methods and apparatus to insert prefetch instructions based on garbage collector analysis and compiler analysis are disclosed. In an example method, one or more batches of samples associated with cache misses from a performance monitoring unit in a processor system are received. One or more samples from the one or more batches of samples based on delinquent information are selected. A performance impact indicator associated with the one or more samples is generated. Based on the performance indicator, at least one of a garbage collector analysis and a compiler analysis is initiated to identify one or more delinquent paths. Based on the at least one of the garbage collector analysis and the compiler analysis, one or more prefetch points to insert prefetch instructions are identified.
