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1.发明公开Apparatus and method for controlling a digital speech filing and retrieval system during playback mode 失效装置和方法用于在播放期间用于记录和语音的再现的数字系统的控制。
公开(公告)号：EP0160788A2
公开(公告)日：1985-11-13
申请号：EP85101522.2
申请日：1985-02-13
IPC分类号： H04M1/65
CPC分类号： H04M1/652
摘要： An improved method and apparatus for digital speech storage and retrieval systems is described which disconnects the parallel tone receiver from the reception path of the hybrid circuit during the active playback of previously recorded material. This prevents interference with incoming control signals by feedback of signals through the hybrid circuit that occurs during playback of the stored speech. A diverter switch is controlled during the playback mode to allow incoming control signals to be decoded only when gaps of sufficient length are detected in the played back program.
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公开(公告)号：EP0198216B1
公开(公告)日：1994-06-22
申请号：EP86103214.2
申请日：1986-03-11
CPC分类号： G06F9/3889 , G06F9/3861 , G06F17/10
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公开(公告)号：EP0198214B1
公开(公告)日：1993-02-03
申请号：EP86103207.6
申请日：1986-03-11
CPC分类号： G06F17/10 , G06F9/3842
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4.发明公开Branch control in a three phase pipelined signal processor 失效einem Dreiphasen-Pipeline-Signalprozessor的Verzweigungssteuerung。
公开(公告)号：EP0198214A2
公开(公告)日：1986-10-22
申请号：EP86103207.6
申请日：1986-03-11
CPC分类号： G06F17/10 , G06F9/3842
摘要： The architecture and instructions of the processor utilized in the present invention permit efficient accomplishment of signal processing tasks. A three phase pipelined operation for instructions exists consisting of fetch, decode, and execute operations. To provide additional flexibility and reduce branch latency, all of the instructions executed except for branch instructions are executed on phase three. Branch instructions are caused to execute at the end of phase two. The branching conditions may be on the basis of "hot bits" existing within the processor during the second cycle and resulting from the execution of the instruction just preceding the branch instruction. Conditional branches are performed based upon conditions not previously latched into registers that result from the execution of such instructions. These conditions are generated at the Isame time that the branch will be executed. The conditions which may be used to trigger a branching decision may also result from the ALU operation output or from the state of a selected data bus bit. jThe instructions providing the branch conditions must not be separated from the associated branch instruction. Therefore, to prevent separation of these two instructions, interrupt protection is always provided for such sequences. Indirect branching is also accommodated by making available the contents of a common data bus to be placed in the instruction address register that would be branched to. The contents of the data bus depend upon the instruction which executes simultaneously with the branch instruction, i.e., that which is in the third phase in the pipeline. Interrupt protection is therefore required for these types of branching actions as well.
摘要翻译： 在本发明中使用的处理器的架构和指令允许有效地完成信号处理任务。 用于指令的三相流水线操作包括获取，解码和执行操作。 为了提供额外的灵活性并减少分支延迟，除了分支指令之外执行的所有指令都在第三阶段执行。 分支指令在第二阶段结束时执行。 分支条件可以基于在第二周期期间在处理器内存在的“热位”，并且是由于执行在分支指令之前的指令而导致的。 条件分支是根据执行这些指令而导致的先前未被锁存到寄存器中的条件执行的。 这些条件是在分支执行的同时生成的。 可以用于触发分支决定的条件也可以由ALU操作输出或从所选择的数据总线位的状态产生。 提供分支条件的指令不能与关联的分支指令分离。 因此，为了防止这两个指令的分离，始终为这样的序列提供中断保护。 间接分支也可以通过提供待分配到指令地址寄存器中的公共数据总线的内容来实现。 数据总线的内容取决于与分支指令同时执行的指令，即在流水线中处于第三阶段的指令。 因此，这些类型的分支动作也需要使用中断保护。
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5.发明授权Apparatus and method for controlling a digital speech filing and retrieval system during playback mode 失效在播放模式下控制数字播放和检索系统的装置和方法
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公开(公告)号：EP0198216A3
公开(公告)日：1989-12-06
申请号：EP86103214.2
申请日：1986-03-11
CPC分类号： G06F9/3889 , G06F9/3861 , G06F17/10
摘要： This processor is a single chip implementation of an architecture that is designed to expeditiously handle certain tasks commonly associated with signal processing. Sequential multiply and accumulate operations, in particular, can be accomplished quite efficiently. The processor is pipelined in two areas. Instructions are passed through a three phase pipeline and consist of fetch, decode and execute, while the multiplier utilizes a two phase pipeline. The data flow is parallel and of 16-bit width throughout. The instruction store is maintained separately from the data store and provisions are included for having the processor enabled to read and write its own instruction store. Some parallel or compound instructions are implemented to permit transfer actions such as storage or I/O to or from instruction registers to occur concurrently with a compute action in different segments of the data flow. The arithmetic capabilities of the processor include both the separate multiplier and a full arithmetic logic unit. Two DMA modes are permitted. Extensive diagnostic capabilities, some of which utilize the processor's ability to read and write its own instruction store, are also included.
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公开(公告)号：EP0198214A3
公开(公告)日：1989-12-06
申请号：EP86103207.6
申请日：1986-03-11
CPC分类号： G06F17/10 , G06F9/3842
摘要： The architecture and instructions of the processor utilized in the present invention permit efficient accomplishment of signal processing tasks. A three phase pipelined operation for instructions exists consisting of fetch, decode, and execute operations. To provide additional flexibility and reduce branch latency, all of the instructions executed except for branch instructions are executed on phase three. Branch instructions are caused to execute at the end of phase two. The branching conditions may be on the basis of "hot bits" existing within the processor during the second cycle and resulting from the execution of the instruction just preceding the branch instruction. Conditional branches are performed based upon conditions not previously latched into registers that result from the execution of such instructions. These conditions are generated at the Isame time that the branch will be executed. The conditions which may be used to trigger a branching decision may also result from the ALU operation output or from the state of a selected data bus bit. jThe instructions providing the branch conditions must not be separated from the associated branch instruction. Therefore, to prevent separation of these two instructions, interrupt protection is always provided for such sequences. Indirect branching is also accommodated by making available the contents of a common data bus to be placed in the instruction address register that would be branched to. The contents of the data bus depend upon the instruction which executes simultaneously with the branch instruction, i.e., that which is in the third phase in the pipeline. Interrupt protection is therefore required for these types of branching actions as well.
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公开(公告)号：EP0198216A2
公开(公告)日：1986-10-22
申请号：EP86103214.2
申请日：1986-03-11
CPC分类号： G06F9/3889 , G06F9/3861 , G06F17/10
摘要： This processor is a single chip implementation of an architecture that is designed to expeditiously handle certain tasks commonly associated with signal processing. Sequential multiply and accumulate operations, in particular, can be accomplished quite efficiently. The processor is pipelined in two areas. Instructions are passed through a three phase pipeline and consist of fetch, decode and execute, while the multiplier utilizes a two phase pipeline. The data flow is parallel and of 16-bit width throughout. The instruction store is maintained separately from the data store and provisions are included for having the processor enabled to read and write its own instruction store. Some parallel or compound instructions are implemented to permit transfer actions such as storage or I/O to or from instruction registers to occur concurrently with a compute action in different segments of the data flow. The arithmetic capabilities of the processor include both the separate multiplier and a full arithmetic logic unit. Two DMA modes are permitted. Extensive diagnostic capabilities, some of which utilize the processor's ability to read and write its own instruction store, are also included.
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9.发明授权
公开(公告)号：EP0324308B1
公开(公告)日：1996-03-27
申请号：EP88480070.7
申请日：1988-11-08
发明人： Larsen, Larry Donald
IPC分类号： G06F9/30
CPC分类号： G06F9/3822 , G06F9/30 , G06F9/30145 , G06F9/30167 , G06F9/30174 , G06F9/30185 , G06F9/30196
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公开(公告)号：EP0324308A3
公开(公告)日：1991-03-27
申请号：EP88480070.7
申请日：1988-11-08
发明人： Larsen, Larry Donald
IPC分类号： G06F9/30
CPC分类号： G06F9/3822 , G06F9/30 , G06F9/30145 , G06F9/30167 , G06F9/30174 , G06F9/30185 , G06F9/30196
摘要： This invention relates to the architectural design of a data processing system and its method of operation which permits normally incompatible plural format instructions for dissimilar processors to be placed intermixed in the instruction storage of a single machine but to be accurately decoded and executed properly regardless. Instructions in different formats which are normally incompatible, are placed in predefined or segregated areas of the instruction store (2). Instructions are fetched and decoded in an instruction decode memory (5) in a manner which uses portions of both the fetched-from address in the instruction (2) store and the instruction itself. Decoding is thus determined in part by where in the instruction store the instruction resided when fetched, and by the specific instruction itself. This approach is compatible with both ordinary processor architecture and with pipelined processor architectures.
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