LOW COMPLEXITY MULTIUSER DETECTOR
    1.
    发明公开
    LOW COMPLEXITY MULTIUSER DETECTOR 审中-公开
    更多用户检测低复杂度

    公开(公告)号:EP1446892A1

    公开(公告)日:2004-08-18

    申请号:EP02783365.6

    申请日:2002-11-07

    IPC分类号: H04B1/707 H04L25/02

    CPC分类号: H04B1/71055 H04L25/0232

    摘要: A multi-user detector for use in a CDMA receiver system includes a channel tap interpolator to generate interpolated channel taps for users of interest. The interpolated channel taps occur at integer multiples of a chip period from a sampling reference point. The channel tap interpolation allows detection processing to proceed in the chip domain, rather than in the sample domain, thus reducing the complexity of the multi-user solution significantly. In at least one approach, a number of low dimensionality 'virtual' users are defined based on the recursive property of the spreading sequences. Solutions may then be developed for the virtual users using conventional detection (e.g., MMSE) techniques.

    CYCLIC ADAPTIVE RECEIVERS FOR DS-CDMA SIGNALS
    2.
    发明公开
    CYCLIC ADAPTIVE RECEIVERS FOR DS-CDMA SIGNALS 有权
    循环可调接收机DS-CDMA信号

    公开(公告)号:EP1034621A1

    公开(公告)日:2000-09-13

    申请号:EP99946409.2

    申请日:1999-09-15

    IPC分类号: H04B1/707

    CPC分类号: H04B1/7105

    摘要: In a receiver (100) receiving a signal (RECEIVED SIGNAL), the signal including data which is at least modulated by a cyclic sequence, a method for operating the receiver (100), the method including the steps of receiving a portion of the signal (RECEIVED SIGNAL), the portion being modulated by a predetermined section of the cyclic sequence, receiving an additional portion of the signal (RECEIVED SIGNAL), the additional portion being modulated by the predetermined section of the cyclic section, jointly processing (102A-102K) the portion and the additional portion and producing a set of receiver parameters, the receiver parameters minimizing a predetermined cost function for the predetermined section of the cyclic sequence.

    METHOD AND APPARATUS OF PILOT SIGNAL SYNCHRONIZATION VERIFIER
    3.
    发明授权
    METHOD AND APPARATUS OF PILOT SIGNAL SYNCHRONIZATION VERIFIER 有权
    方法和装置进行确认的导频信号的同步

    公开(公告)号:EP1440522B1

    公开(公告)日:2006-12-20

    申请号:EP02772783.3

    申请日:2002-09-23

    IPC分类号: H04B1/707

    CPC分类号: H04B1/70755

    摘要: A method comprising verifing synchronisation of a pilot signal pattern by comparing a sun of dot products 133 of a first and a second demodulated received symbols calculated over pairs of consecutive demodulated received symbols, wherein the dot products of the transmitted pilot signal at a first time index and at a second consecutive time index of the demodulated received symbols comprise substantially equal values for the pilot signal pattern.

    METHOD AND APPARATUS OF PILOT SIGNAL SYNCHRONIZATION VERIFIER
    6.
    发明公开
    METHOD AND APPARATUS OF PILOT SIGNAL SYNCHRONIZATION VERIFIER 有权
    方法和装置进行确认的导频信号的同步

    公开(公告)号:EP1440522A1

    公开(公告)日:2004-07-28

    申请号:EP02772783.3

    申请日:2002-09-23

    IPC分类号: H04B1/707

    CPC分类号: H04B1/70755

    摘要: A method comprising verifing synchronisation of a pilot signal pattern by comparing a sun of dot products (133) of a first and a second demodulated received symbols calculated over pairs of consecutive demodulated received symbols, wherein the dot products of the transmitted pilot signal at a first time index and at a second consecutive time index of the demodulated received symbols comprise substantially equal values for the pilot signal pattern.

    VOICE-CHANNEL FREQUENCY SYNCHRONIZATION
    7.
    发明公开
    VOICE-CHANNEL FREQUENCY SYNCHRONIZATION 失效
    语音信道频率同步

    公开(公告)号:EP0986858A1

    公开(公告)日:2000-03-22

    申请号:EP98924540.2

    申请日:1998-06-04

    IPC分类号: H04B1/10

    摘要: A synchronized frequency generating system (100) comprises a main crystal clock (102), for producing a basic frequency FB, a channel sampling phase locked loop (PLL) unit (104) connected to the main crystal clock, for converting the basic frequency FB into a channel sampling frequency FCS, a voice sampling PLL unit (108) connected to the main crystal clock (102), for converting the basic frequency FB into a voice sampling frequency FVS, a time tracking unit (106) connected to the channel sampling PLL unit (104), for detecting signal characteristics so as to determine a channel sampling frequency phase change value and a frame timing phase change value, and a phase controller (110) connected to the voice sampling PLL. The phase controller (110) receives channel sampling frequency phase adjustment data and determines a voice sampling frequency phase change value. The phase controller (110) provides the voice sampling frequency phase change value to the voice sampling PLL.

    摘要翻译: 一种同步频率产生系统(100),包括:用于产生基本频率FB的主晶体时钟(102);连接到主晶体时钟的信道采样锁相环(PLL)单元(104),用于将基频FB 转换成信道采样频率FCS;连接到主晶体时钟(102)的语音采样PLL单元(108),用于将基本频率FB转换为语音采样频率FVS;时间跟踪单元(106),连接到信道采样 PLL单元(104),用于检测信号特性以确定信道采样频率相位改变值和帧定时相位改变值;以及相位控制器(110),连接到语音采样PLL。 相位控制器(110)接收信道采样频率相位调整数据并确定话音采样频率相位改变值。 相位控制器(110)将语音采样频率相位改变值提供给语音采样PLL。