公开(公告)号：EP3723330B1

公开(公告)日：2024-07-31

申请号：EP19894659.2

申请日：2019-12-13

IPC: G11C15/04 ,  G06F9/30 ,  G06F9/38 ,  H04L45/745

CPC classification number: G11C15/04 ,  G06F9/30047 ,  G06F9/3851 ,  G06F9/3802 ,  G06F9/30061 ,  H04L45/74591

公开(公告)号：EP1735698A4

公开(公告)日：2008-11-19

申请号：EP05730402

申请日：2005-03-29

Applicant: SUN MICROSYSTEMS INC

Inventor： TREMBLAY MARC ,  CHAUDHRY SHAILENDER ,  JACOBSON QUINN A

IPC: G06F9/30 ,  G06F9/32 ,  G06F9/38

CPC classification number: G06F9/30061 ,  G06F9/383 ,  G06F9/3838 ,  G06F9/3842

Abstract: A user is provided with means to sample memory hierarchy via software. This allows a user to enhance memory-level parallelism via software. A status of information needed for execution of a second computer program instruction is read in response to execution (301) of a first computer program instruction. Execution continues with execution of a second computer program instruction upon the status being a first status (303). Alternatively, a third computer program instruction is executed (304) upon the status being a second status different from the first status. Thus, execution of the first computer program instruction allows control of the memory hierarchy, which in turn give the user control of the memory hierarchy.

公开(公告)号：EP1383038A4

公开(公告)日：2008-10-15

申请号：EP02720577

申请日：2002-04-23

Applicant: NTI INC

Inventor： NAKAMURA TAKATOSHI ,  YOKOTA AKIHIRO

IPC: G06F7/544 ,  G06F7/00

CPC classification number: G06F9/30061 ,  G06F9/30094

Abstract: A calculation apparatus outputting a calculation result in accordance with an input condition and capable of increasing the processing speed. As a data of an address corresponding to an input condition of an calculation formula, its calculation result is stored in a memory and when the input condition is input to the memory, the calculation result is output. Moreover, the calculation apparatus executes calculation of a predetermined calculation formula and by learning, can output a calculation result at a high speed with a simple configuration. Storage means for outputting data corresponding to an address stores a calculation formula in which input is correlated to an address and output is correlated to data, and the calculation formula is selectively stored in accordance with the use frequency of the calculation formula.

公开(公告)号：EP1310864A2

公开(公告)日：2003-05-14

申请号：EP02028088.9

申请日：1997-05-28

Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

Inventor： Yasoshima, Hiroyuki ,  Kabuo, Hideyuki

IPC: G06F9/38

CPC classification number: G06F9/30094 ,  G06F9/30061 ,  G06F9/3842

Abstract: A method of controlling the rewriting of a conditional flag in a processor comprises a first step of determining, when an instruction involving the rewriting of the conditional flag is executed, whether the rewriting of the conditional flag is enabled or disabled based on the order of instructions in a program. This method further comprises a second step of rewriting, when the rewriting of the conditional flag is enabled, the conditional flag in executing said instruction or not rewriting, when the rewriting of the conditional flag is disabled, the conditional flag in executing said instruction.

Abstract translation: 控制处理器中的条件标志的重写的方法包括：第一步骤，当执行涉及重写条件标志的指令时，基于指令的顺序来确定条件标志的重写是启用还是禁用 在程序中。 该方法还包括第二步骤，当条件标志的重写被使能时，重写条件标志的条件标志在执行所述指令或不重写时，条件标志的重写被禁用时执行所述指令的条件标志。

公开(公告)号：EP0992890A3

公开(公告)日：2000-04-19

申请号：EP99400554.4

申请日：1999-03-08

Applicant: TEXAS INSTRUMENTS INC. ,  TEXAS INSTRUMENTS FRANCE

Inventor： Laurenti, Gilbert ,  Djafarian, Karim ,  Ponsot, Eric ,  Boyodjian, Alain ,  Gillet, Vincent

IPC: G06F9/32

CPC classification number: G06F7/764 ,  G06F5/01 ,  G06F7/607 ,  G06F7/74 ,  G06F7/762 ,  G06F9/30061 ,  G06F9/30065 ,  G06F9/30072 ,  G06F9/325

Abstract: A processing engine is described having an execution mechanism which may be configured to modify a value whilst a condition is true. The execution mechanism switches the processing engine to one of a plurality of tasks for the condition becoming false. Preferably, the value is a repeat loop counter value or a data value modified during a repeat loop.

公开(公告)号：EP0448127B1

公开(公告)日：1998-01-28

申请号：EP91106315.4

申请日：1985-05-07

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Moller, Ole Henrik ,  Sanjay, Iyer ,  Chu, Paul Po Loi

IPC: G06F9/26

CPC classification number: G06F9/264 ,  G06F9/268 ,  G06F9/30061 ,  G06F11/34 ,  G06F11/3648 ,  G06F13/24

公开(公告)号：EP0778519A2

公开(公告)日：1997-06-11

申请号：EP96308514.7

申请日：1996-11-26

Applicant: SUN MICROSYSTEMS, INC.

Inventor： Yung, Robert

IPC: G06F9/38

CPC classification number: G06F9/3865 ,  G06F9/30061 ,  G06F9/3842 ,  G06F9/3859

Abstract: A microprocessor with a dispatch unit which dispatches a maximum number of instructions each cycle, without splitting into separate blocks after a branch instruction. A mispredicted branch is handled by setting a valid bit to invalid for instructions following the branch instruction in an outstanding instruction FIFO.

Abstract translation: 具有调度单元的微处理器，每个周期调度最大数量的指令，而不会在分支指令之后分割成单独的块。 通过将未完成的指令FIFO中的分支指令之后的指令的有效位设置为无效来处理错误的分支。

公开(公告)号：EP0207519B1

公开(公告)日：1993-12-15

申请号：EP86109096.7

申请日：1986-07-03

Applicant: HITACHI, LTD. ,  Hitachi Engineering Co., Ltd.

Inventor： Yamaguchi, Shinichiro ,  Matsumoto, Hidekazu ,  Bandoh, Tadaaki ,  Nakanishi, Hiroaki ,  Hirose, Kenzi ,  Kobayashi, Takao ,  Miyazaki, Yoshihiro

IPC: G06F9/30 ,  G06F9/44

CPC classification number: G06F9/30181 ,  G06F9/30061 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/30192 ,  G06F9/3557 ,  G06F9/4496

Abstract: A data processor (100) for execution of tagged data and tagless data has a decoder (130) for discriminating whether the data is tagged or tagless one and in case of a tagged data, separates a tag part and uses the remaining part for address computation. The data processor also comprises a unit for evaluating the tag part and a micro program controller (290) for multi-branching in accordance with the evaluation result of the tag part. The tag evaluating unit includes an extender eliminating part (250) for extracting the tag part from data on a data bus (340), a plurality of tag part storing registers (260, 270) for storing the tag part from the eliminating part under the control of the micro program controller, and a tag multi-way jump encoder (292) for generating a tag multi-way jump address to feed it to the controller on the basis of the outputs of the registers and a signal from the micro program controller, thereby enabling tag multi-way jump.

公开(公告)号：EP0167241B1

公开(公告)日：1993-12-15

申请号：EP85303224.1

申请日：1985-05-07

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Moller, Ole Henrik ,  Sanjay, Iyer ,  Chu, Paul Po Loi

IPC: G06F9/26 ,  G06F11/00 ,  G06F13/24

CPC classification number: G06F9/264 ,  G06F9/268 ,  G06F9/30061 ,  G06F11/34 ,  G06F11/3648 ,  G06F13/24

公开(公告)号：EP0448127A2

公开(公告)日：1991-09-25

申请号：EP91106315.4

申请日：1985-05-07

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Moller, Ole Henrik ,  Sanjay, Iyer ,  Chu, Paul Po Loi

IPC: G06F9/26

CPC classification number: G06F9/264 ,  G06F9/268 ,  G06F9/30061 ,  G06F11/34 ,  G06F11/3648 ,  G06F13/24

Abstract: A one-chip, integrated-circuit, microprogram sequence controller for use in a microprogrammed system having a data processing unit and a microprogram memory, that controls the order and execution of microinstructions within the microprogram memory. The controller is provided with two 16-bit microinstruction address input busses and a 16-bit output bus on which microinstruction addresses are issued to the microprogram memory. One of the input busses and the output busses are bidirectional providing access to various on-chip parameters such as the contents of the top of an on-chip stack memory or the value of an on-chip stack pointer. An on-chip comparator permits trapping of a microinstruction at a specified address or gathering of run-time statistics. A structured, 64-element instruction set is provided which includes sixteen special-function continue instructions which perform additional operations without imposing added time requirements. A set of multiway instructions are provided affording selection of alternative multiway branch addresses from four 4-bit data inputs to the controller.

Abstract translation: 用于具有数据处理单元和微程序存储器的微程序系统的单芯片集成电路微程序序列控制器，其控制微程序存储器内的微指令的顺序和执行。 该控制器具有两个16位微指令地址输入总线和一个16位输出总线，微指令地址向微程序存储器发出。 输入总线和输出总线中的一个是双向的，提供对诸如片上堆栈存储器的顶部的内容或片上堆栈指针的值的各种片上参数的访问。 片上比较器允许在指定地址捕获微指令或收集运行时统计信息。 提供了一个结构化的64元素指令集，其中包括十六个特殊功能的继续指令，执行附加操作，而不需要增加时间要求。 提供一组多路指令，提供从四个4位数据输入到控制器的替代多路分支地址的选择。