公开(公告)号：EP3343594A3

公开(公告)日：2018-09-19

申请号：EP17205253.2

申请日：2017-12-04

Applicant: Renesas Electronics Corporation

Inventor： SATO, Yoshiaki ,  KARIYAZAKI, Shuuichi ,  NAKAGAWA, Kazuyuki

IPC: H01L21/66 ,  H01L23/498 ,  H05K1/02 ,  H05K1/18

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/565 ,  H01L22/32 ,  H01L23/3157 ,  H01L23/367 ,  H01L23/3675 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H01L23/642 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19103 ,  H05K1/0231 ,  H05K1/0268 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/10015 ,  H01L2924/00014

Abstract: A semiconductor device which provides improved reliability. The semiconductor device includes: a wiring substrate having a first surface and a second surface opposite to the first surface; a chip condenser built in the wiring substrate, having a first electrode and a second electrode; a first terminal and a second terminal disposed on the first surface; and a third terminal disposed on the second surface. The semiconductor device further includes: a first conduction path for coupling the first terminal and the third terminal; a second conduction path for coupling the first terminal and the first electrode; a third conduction path for coupling the third terminal and the first electrode; and a fourth conduction path for coupling the second terminal and the first electrode.

公开(公告)号：EP3358617A1

公开(公告)日：2018-08-08

申请号：EP18154661.5

申请日：2018-02-01

Applicant: JTEKT Corporation

Inventor： TANI, Naoki

IPC: H01L23/485 ,  H01L23/488 ,  H01L21/60 ,  H01L27/105

CPC classification number: H01L23/36 ,  H01L23/488 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L29/4238 ,  H01L2224/13013 ,  H01L2224/131 ,  H01L2224/14051 ,  H01L2224/14151 ,  H01L2224/14156 ,  H01L2224/14517 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/29013 ,  H01L2224/291 ,  H01L2224/30051 ,  H01L2224/30151 ,  H01L2224/30156 ,  H01L2224/30517 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/33051 ,  H01L2224/33181 ,  H01L2224/73253 ,  H01L2224/81801 ,  H01L2224/81825 ,  H01L2224/83801 ,  H01L2224/83825 ,  H01L2924/3511 ,  H02K9/22 ,  H02K11/33 ,  H05K1/0201 ,  H05K2201/10439 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: An electrode surface (32a, 35a) of a horizontal semiconductor chip (32, 35) and a substrate (31) are joined together through a plurality of first joint portions (50, 70) including a plurality of joint portions (7, 51, 71) at which a plurality of electrodes (D, S, G) formed on the electrode surface (32a, 35a) are joined to the substrate (31). A no-electrode surface (32b, 35b) of the horizontal semiconductor chip (32, 35) and a heatsink (33) are joined together through a second joint portion (8) at which the no-electrode surface (32b, 35b) and the heatsink (33) are joined together. In a plan view from a direction normal to a principal surface of the substrate (31), the region defined by the outline of a rough shape of an aggregate of the first joint portions (50, 70) and the region defined by the outline of the second joint portion (8) are the same in position, shape, and size. Accordingly, the tensile forces acting on the no-electrode surface (32b, 35b) and the electrode surface (32a, 35a) of the horizontal semiconductor chip (32, 35) are substantially equal. Thus, warping of the horizontal semiconductor chip (32, 35) can be suppressed.
The first joint portions (50, 70) may optionally include one or more dummy joint portions (52, 53, 54, 72, 73, 74) at which the electrode surface (32a, 35a) and the substrate (31) are joined together, without electrical connection of the chip electrodes to the circuit wiring of the substrate (31) at the dummy joint portions (52, 53, 54, 72, 73, 74).

公开(公告)号：EP3150672B1

公开(公告)日：2018-05-09

申请号：EP16190314.1

申请日：2016-09-23

Applicant: Shin-Etsu Chemical Co., Ltd.

Inventor： AKIBA, Shota ,  TSUJI, Kenichi ,  YAMADA, Kunihiro

IPC: C08L83/04 ,  C08K3/08

CPC classification number: C09K5/14 ,  C08F290/068 ,  C08G77/12 ,  C08G77/20 ,  C08K3/08 ,  C08K2003/0806 ,  C08K2201/001 ,  C08L83/00 ,  C08L83/04 ,  C08L2666/54 ,  H01L23/3675 ,  H01L23/3737 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/16225 ,  H01L2224/29291 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83203 ,  H01L2924/0715 ,  H01L2924/1432 ,  H01L2924/00 ,  C08F230/08

Abstract: Provided is a thermal conductive silicone composition having a superior thermal conductivity. The thermal conductive silicone composition contains: (A) an organopolysiloxane that exhibits a kinetic viscosity of 10 to 100,000 mm 2 /s at 25°C, and is represented by the following average composition formula (1) €ƒ€ƒ€ƒ€ƒ€ƒ€ƒ€ƒ€ƒ R 1 a SiO (4-a)/2 €ƒ€ƒ€ƒ€ƒ€ƒ(1) wherein R 1 represents a hydrogen atom or at least one group selected from a hydroxy group and a saturated or unsaturated monovalent hydrocarbon group having 1 to 18 carbon atoms, and a satisfies 1.8 ‰¤ a ‰¤ 2.2; and (B) a silver powder having a tap density of not lower than 3.0 g/cm 3 and a specific surface area of not larger than 2.0 m 2 /g, such silver powder being in an amount of 300 to 11,000 parts by mass with respect to 100 parts by mass of the component (A).

公开(公告)号：EP3093886B1

公开(公告)日：2018-03-21

申请号：EP16166286.1

申请日：2016-04-20

Applicant: Honeywell International Inc.

Inventor： KATTI, Romney R. ,  TUCKER, James L.

IPC: H01L25/065 ,  H01L23/552 ,  H01L21/98 ,  H01L21/60

CPC classification number: H01L23/49575 ,  H01L21/4825 ,  H01L21/4871 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49568 ,  H01L23/552 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/80 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04 ,  H01L2224/04042 ,  H01L2224/05647 ,  H01L2224/06135 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48464 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48472 ,  H01L2224/49109 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/80203 ,  H01L2224/80447 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/8148 ,  H01L2224/81484 ,  H01L2224/81801 ,  H01L2224/83801 ,  H01L2224/85424 ,  H01L2224/85439 ,  H01L2224/85447 ,  H01L2224/8548 ,  H01L2224/85484 ,  H01L2224/92165 ,  H01L2224/9222 ,  H01L2224/92247 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06537 ,  H01L2225/06562 ,  H01L2225/06575 ,  H01L2225/06589 ,  H01L2225/06593 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/1435 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2224/32145 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2224/80 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2224/32245 ,  H01L2224/48247

Abstract: A stacked integrated circuit (IC) system including a substrate, a contour support, and a first and second IC dies. The contour support including a first support frame attached to the substrate defining a first lateral contact surface substantially orthogonal to the substrate, a support plate on the first support frame substantially parallel to the substrate, and a second support frame on the support plate defining a second lateral contact surface substantially orthogonal to the substrate, with the first and second lateral contact surfaces laterally offset from each other. The first integrated circuit die with a side abutting the first lateral contact surface, the second integrated circuit die with a side abutting the second lateral contact surface such that at least a portion of the support plate is between the first and second integrated circuit dies.

公开(公告)号：EP3281218A1

公开(公告)日：2018-02-14

申请号：EP16726297.1

申请日：2016-05-23

Applicant: Siemens Aktiengesellschaft

Inventor： STEGMEIER, Stefan ,  BAUEREGGER, Hubert ,  SOMMER, Volkmar

IPC: H01L21/60 ,  H01L23/492 ,  H01L23/495 ,  H01L23/367

CPC classification number: H01L23/49 ,  C25D3/38 ,  C25D5/18 ,  C25D21/14 ,  H01L23/3733 ,  H01L23/3735 ,  H01L23/4922 ,  H01L23/49513 ,  H01L23/49537 ,  H01L23/49562 ,  H01L23/49568 ,  H01L23/49811 ,  H01L23/50 ,  H01L24/05 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/75 ,  H01L24/77 ,  H01L24/82 ,  H01L24/83 ,  H01L24/84 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/04026 ,  H01L2224/04034 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/24105 ,  H01L2224/24227 ,  H01L2224/24245 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/3207 ,  H01L2224/32227 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/37005 ,  H01L2224/37111 ,  H01L2224/37124 ,  H01L2224/37139 ,  H01L2224/37144 ,  H01L2224/37147 ,  H01L2224/37155 ,  H01L2224/37166 ,  H01L2224/3719 ,  H01L2224/37211 ,  H01L2224/37224 ,  H01L2224/37239 ,  H01L2224/37244 ,  H01L2224/37247 ,  H01L2224/37255 ,  H01L2224/37266 ,  H01L2224/3729 ,  H01L2224/373 ,  H01L2224/37395 ,  H01L2224/376 ,  H01L2224/4007 ,  H01L2224/40227 ,  H01L2224/40499 ,  H01L2224/756 ,  H01L2224/75703 ,  H01L2224/776 ,  H01L2224/77703 ,  H01L2224/821 ,  H01L2224/82101 ,  H01L2224/83007 ,  H01L2224/831 ,  H01L2224/834 ,  H01L2224/83411 ,  H01L2224/83424 ,  H01L2224/83439 ,  H01L2224/83444 ,  H01L2224/83447 ,  H01L2224/83455 ,  H01L2224/83466 ,  H01L2224/8349 ,  H01L2224/83511 ,  H01L2224/83524 ,  H01L2224/83539 ,  H01L2224/83544 ,  H01L2224/83547 ,  H01L2224/83555 ,  H01L2224/83566 ,  H01L2224/8359 ,  H01L2224/836 ,  H01L2224/83695 ,  H01L2224/8385 ,  H01L2224/83907 ,  H01L2224/84007 ,  H01L2224/841 ,  H01L2224/8485 ,  H01L2224/8492 ,  H01L2224/84951 ,  H01L2224/9201 ,  H01L2224/9205 ,  H01L2224/9221 ,  H01L2224/97 ,  H01L2924/13055 ,  H01L2924/181 ,  H05K3/424 ,  H01L2924/00012 ,  H05K3/4661 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01028 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/0105 ,  H01L2224/83 ,  H01L2224/84 ,  H01L2224/82 ,  H01L2924/01014

Abstract: The invention relates to a method for electrically contacting a component (10) (for example a power component and/or a (semiconductor) component having at least one transistor, preferably an IGBT (insulated-gate bipolar transistor)) having at least one contact (40, 50), at least one open-pored contact piece (60, 70) is galvanically (electrochemically or free of external current) connected to at least one contact (40, 50). In this way, a component module is achieved. The contact (40, 50) is preferably a flat part or has a contact surface, the largest planar extent thereof being greater than an extension of the contact (40, 50) perpendicular to said contact surface. The temperature of the galvanic connection is at most 100 °C, preferably at most 60 °C, advantageously at most 20 °C and ideally at most 5 °C and/or deviates from the operating temperature of the component by at most 50 °C, preferably by at most 20 °C, in particular by at most 10 °C and ideally by at most 5 °C, preferably by at most 2 °C. The component (10) can be contacted by means of the contact piece (60, 70) with a further component, a current conductor and/or a substrate (90). Preferably, a component (10) having two contacts (40, 50) on opposite sides of the component (10) is used, wherein at least one open-pored contact piece (60, 70) is galvanically connected to each contact (40, 50).

公开(公告)号：EP3082243A4

公开(公告)日：2017-12-06

申请号：EP14870416

申请日：2014-12-12

Applicant: HITACHI POWER SEMICONDUCTOR DEVICE LTD

Inventor： ISHIMARU TETSUYA ,  MORI MUTSUHIRO ,  SAKANO JUNICHI ,  ONDA KOHHEI

IPC: H01L23/051 ,  H01L23/31 ,  H01L23/367 ,  H01L23/488 ,  H01L23/544 ,  H01L25/07 ,  H02M7/219

CPC classification number: H01L29/7808 ,  H01L23/051 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/3142 ,  H01L23/367 ,  H01L23/373 ,  H01L23/544 ,  H01L24/01 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/66 ,  H01L24/69 ,  H01L24/73 ,  H01L24/75 ,  H01L24/78 ,  H01L24/83 ,  H01L24/84 ,  H01L24/85 ,  H01L24/92 ,  H01L25/07 ,  H01L25/072 ,  H01L29/7805 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/291 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/37012 ,  H01L2224/37147 ,  H01L2224/40137 ,  H01L2224/40499 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48499 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2224/75754 ,  H01L2224/78753 ,  H01L2224/78802 ,  H01L2224/83101 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2224/9221 ,  H01L2924/00011 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/19107 ,  H02K11/00 ,  H02K11/046 ,  H02K19/36 ,  H02M1/08 ,  H02M7/003 ,  H02M7/217 ,  H02M7/219 ,  H02M2001/0006 ,  H02P9/00 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/01005 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2224/83 ,  H01L2224/84

Abstract: The semiconductor device (S1) has a first external electrode (101) having an outer peripheral section (101s), which has a circular shape in top plan view and which is to be attached to an alternator (Ot). On the first external electrode (101) there mounted: a MOSFET chip (103); a control circuitry (104) to which voltages at or a current flowing between a first main terminal (103d) and a second main terminal (103s) of the MOSFET chip (103) is inputted and which generates, on the basis of the voltages or the current, a control signal applied to a gate (103g) of the MOSFET chip(103); and a capacitor (105) for providing a power supply to the control circuitry (104). The semiconductor device further has a second external electrode (107) disposed opposite to the first external electrode with respect to the MOSFET chip (103). An electrical connection is made between the first main terminal (103d) of the MOSFET chip (103) and the first external electrode (101), and between the second main terminal (103s) of the MOSFET chip (103) and the second external electrode (107).

公开(公告)号：EP2472574A3

公开(公告)日：2017-11-29

申请号：EP11192975.8

申请日：2011-12-12

Applicant: Robert Bosch GmbH

Inventor： Wolde-Giorgis, Daniel ,  Sentuerk, Tuncay ,  Sueske, Erik ,  Hohenberger, Bernd ,  Klingler, Markus ,  Kalich, Thomas

IPC: H01L21/60 ,  H01L23/482 ,  H01L23/00

CPC classification number: H01L24/83 ,  H01L24/01 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L2224/02125 ,  H01L2224/04026 ,  H01L2224/05573 ,  H01L2224/2745 ,  H01L2224/29005 ,  H01L2224/29007 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/32245 ,  H01L2224/32503 ,  H01L2224/32507 ,  H01L2224/33181 ,  H01L2224/83825 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01063 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/12036 ,  H01L2924/00

Abstract: Die Erfindung betrifft ein Verfahren zur Herstellung einer Einpressdiode, die einen Sockel, einen Kopfdraht und einen zwischen den Sockel und den Kopfdraht gelöteten Halbleiterchip aufweist. Zunächst wird ein Halbleiterchip bereitgestellt, auf dessen Ober- und Unterseite jeweils eine bleifreie Legierung mit niedrigem Schmelzpunkt abgeschieden ist. Anschließend erfolgt ein Verbinden des Halbleiterchips mit dem Sockel und dem Kopfdraht mittels Diffusionslöten. Des Weiteren weist die Einpressdiode vorzugsweise elastisch und/oder plastisch verformbare Funktionsschichten auf, die im Betrieb durch Temperaturdifferenzen bedingte Beschädigungen des Halbleiterchips und des Lotes verhindern.

Abstract translation: 本发明涉及一种制造压配二极管的方法，该压配二极管具有插座，头线和焊接在该插座和头线之间的半导体芯片。 首先，提供半导体芯片，在每个的顶部和底部沉积低熔点的无铅合金。 随后，通过扩散焊接将半导体芯片连接到基部和头部导线。 此外，压入式二极管优选具有弹性和/或塑性可变形的功能层，其防止在操作期间由于温度差异而导致半导体芯片和焊料的损坏。

公开(公告)号：EP2701192B1

公开(公告)日：2017-11-01

申请号：EP11864059.8

申请日：2011-04-18

Applicant: Mitsubishi Electric Corporation

Inventor： OGA, Takuya ,  KATO, Masaki ,  SUGIHARA, Tsuyoshi

IPC: H01L25/07 ,  H01L23/48 ,  H01L25/18 ,  H02M7/48 ,  B60L11/18 ,  B60L15/00 ,  H01L23/31 ,  H01L23/495 ,  H02K11/00 ,  H01L23/00 ,  H02K11/33

CPC classification number: H01L25/07 ,  B60L11/1803 ,  B60L15/007 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49551 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/05 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/02166 ,  H01L2224/04026 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/27013 ,  H01L2224/291 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/3701 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40137 ,  H01L2224/40247 ,  H01L2224/40249 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48699 ,  H01L2224/73215 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3511 ,  H02K11/33 ,  H02M7/537 ,  Y02T10/645 ,  Y02T10/7005 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: Provided is a semiconductor device including: a first MOS-FET (21) joined to a first base plate (11) via solder; a second MOS-FET (22) joined to a second base plate (12) via solder; a first lead (31) joining the first base plate (11) and the second MOS-FET (22); and a second lead (32) joining the second MOS-FET (22) and a current path member (13) that gives and receives current flowing through the MOS-FETs (21, 22) to and from the outside. The second base plate (12) is more rigid than both the leads (31, 32), a boundary line (D-D) intersects the second base plate (12) without intersecting both the leads (31, 32), the boundary line including a gap portion (52) along which both the MOS-FETs (21, 22) are opposed to each other, extending in the direction in which both the MOS-FETs (21, 22) are not opposed to each other.

公开(公告)号：EP3146563A1

公开(公告)日：2017-03-29

申请号：EP15718847.5

申请日：2015-04-21

Applicant: Robert Bosch GmbH

Inventor： DAVES, Walter ,  KASPER, Knut, Alexander ,  DUERNSTEINER, Silvia ,  RITTNER, Martin ,  GUENTHER, Michael

IPC: H01L25/16

CPC classification number: H01L25/16 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/33 ,  H01L24/83 ,  H01L2224/29139 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/8384 ,  H01L2924/0002 ,  H03K17/567 ,  H01L2924/00

Abstract: The invention relates to a commutation cell (7, 16), comprising at least one electrical capacitor (8), at least one controllable semiconductor switch (9), and at least one semiconductor (10), which is connected in series with the controllable semiconductor switch (9), characterized by three circuit carriers (11, 12, 13) arranged parallel to each other, the controllable semiconductor switch (9) being connected in series with the semiconductor (10) by means of a circuit carrier (12) arranged partially between the controllable semiconductor switch (9) and the semiconductor (10), the two other circuit carriers (11, 13) being connected to each other in an electrically conductive manner by means of an assembly (14) formed by the controllable semiconductor switch (9), the semiconductor (10), and the circuit carrier (12) arranged partially between the controllable semiconductor switch (9) and the semiconductor (10), and wherein the electrical capacitor (8) is connected between the two other circuit carriers (11, 13) separately from the assembly (14).

Abstract translation: 一种换向单元，具有至少一个电容器，至少一个可控半导体开关和至少一个与可控半导体开关串联连接的半导体。 换向单元具有彼此平行放置的三个电路基板。 可控半导体开关经由部分位于可控半导体开关和半导体之间的电路基板与半导体串联连接，并且两个其余的电路基板经由由可控制半导体开关和可控半导体开关构成的子组件以导电方式相互连接 半导体开关，部分位于可控半导体开关和半导体之间的半导体和电路基板，电容器在两个其余的电路基板之间与子组件分开地进行切换。

公开(公告)号：EP3123500A1

公开(公告)日：2017-02-01

申请号：EP15713177.2

申请日：2015-03-26

Applicant: Heraeus Deutschland GmbH & Co. KG

Inventor： BENEDIKT, Michael ,  KREBS, Thomas ,  SCHÄFER, Michael ,  SCHMITT, Wolfgang ,  HINRICH, Andreas ,  KLEIN, Andreas ,  BRAND, Alexander ,  BLEIFUSS, Martin

IPC: H01L21/60 ,  H01L23/495 ,  H01L23/488

CPC classification number: H01L23/49513 ,  H01L21/4821 ,  H01L23/49524 ,  H01L23/49548 ,  H01L23/49551 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/37 ,  H01L24/40 ,  H01L24/83 ,  H01L24/84 ,  H01L24/92 ,  H01L2224/27318 ,  H01L2224/2732 ,  H01L2224/27418 ,  H01L2224/27505 ,  H01L2224/27848 ,  H01L2224/29294 ,  H01L2224/29295 ,  H01L2224/29339 ,  H01L2224/2939 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/352 ,  H01L2224/371 ,  H01L2224/37639 ,  H01L2224/4005 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40499 ,  H01L2224/73263 ,  H01L2224/83192 ,  H01L2224/83439 ,  H01L2224/8384 ,  H01L2224/8385 ,  H01L2224/8484 ,  H01L2224/8485 ,  H01L2224/9221 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2224/83 ,  H01L2224/84 ,  H01L2924/00012

Abstract: The invention relates to a carrier (such as a lead frame) and to a clip for at least one semiconductor element which has at least one functional surface (10) for connection to the semiconductor element and a plurality of connections (11). The invention is characterized in that the material of the carrier or of the clip comprises a metal and a layer (12) made of a solidified (dried) sintering paste, in particular a sintering paste containing silver and/or a silver compound, and is arranged on the functional surface (10), wherein the carrier or clip and the layer (12) made of sintering paste form an intermediate product which can be connected to the semiconductor element. The carrier and the clip are used to produce a packaging having a lead frame (lead frame package) by connection to the chip by means of sintering of the solidified sintering pastes in one work step.

Abstract translation: 载体和夹子被用来产生具有由连接到使用固化糊剂烧结的烧结在一个工作步骤中的芯片的引线框的封装。 该载体可以是引线框架和用于至少一个半导体元件的夹子具有用于连接到所述半导体元件和连接的多个至少一个功能面。 载体或夹子的材料包括金属和由固化的烧结膏层。 烧结膏体可以包含银和/或银化合物。 烧结膏被布置在功能面上。 所述载体或夹在中间productsthat制成烧结膏形式的层可以被连接到所述半导体元件。