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    SHIFT REGISTER UNIT AND DRIVING METHOD THEREFOR, GATE DRIVING CIRCUIT AND DISPLAY DEVICE
    2.
    发明公开
    SHIFT REGISTER UNIT AND DRIVING METHOD THEREFOR, GATE DRIVING CIRCUIT AND DISPLAY DEVICE 审中-公开

    公开(公告)号：EP4435789A3

    公开(公告)日：2024-10-30

    申请号：EP24190820.1

    申请日：2018-12-14

    申请人： BOE Technology Group Co., Ltd. ,  Hefei Xinsheng Optoelectronics Technology Co., Ltd

    发明人： FENG, Xuehuan ,  LI, Yongqian

    IPC分类号： G09G3/3266 ,  G11C19/28 ,  G09G3/36

    摘要： A shift register unit, a driving method thereof, a gate driving circuit and a display device. The shift register unit includes a blanking input circuit (100), a display input circuit (200), an output circuit (300), a first control circuit (500) and a second control circuit (600). The blanking input circuit (100) inputs a blanking pull-up signal to a first node (Q) according to a blanking input signal; the display input circuit (200) inputs a display pull-up signal to the first node (Q) in response to a display input signal; the output circuit (300) outputs an composite output signal to an output terminal (Out) under the control of the first node (Q); the first control circuit (500) controls a level of a second node (QB) under the control of the first node (Q); and the second control circuit (600) controls the level of the second node (QB) in response to a blanking pull-down control signal.

    SHIFT REGISTER, GATE DRIVE CIRCUIT, DISPLAY PANEL AND ELECTRONIC DEVICE
    5.
    发明公开
    SHIFT REGISTER, GATE DRIVE CIRCUIT, DISPLAY PANEL AND ELECTRONIC DEVICE 审中-公开

    公开(公告)号：EP4297005A1

    公开(公告)日：2023-12-27

    申请号：EP23735958.3

    申请日：2023-01-04

    申请人： Honor Device Co., Ltd.

    发明人： HAN, Linhong ,  WU, Warming ,  GENG, Di ,  LI, Ling ,  TIAN, Zheng

    IPC分类号： G09G3/20 ,  G09G3/36 ,  G09G3/32 ,  G09G3/3208 ,  G09G3/3266 ,  G11C19/28

    摘要： This application provides a shift register, a gate drive circuit, a display panel, and an electronic device. The shift register includes: a node control module, electrically connected to a first level signal receive end that receives a low level, a second level signal receive end that receives a high level, a first clock signal end, a second clock signal end, a first node, and a second node; an input module, electrically connected to the second clock signal end, a trigger signal input end, and the second node; a voltage regulator module, electrically connected to the second node, a third node, and the second clock signal end; and an output module, electrically connected to the first level signal receive end, the second level signal receive end, a drive signal output end, the first node, and the third node. When a signal output by the drive signal output end is at a low level, a potential of a signal of the third node is less than a potential of the low level received by the first level signal receive end. The node control module includes at least one transistor whose active layer is an oxide semiconductor. At least one of the input module, the voltage regulator module, and the output module includes at least one transistor whose active layer is silicon.

    SHIFT REGISTER, DRIVE CIRCUIT AND DISPLAY SUBSTRATE
    9.
    发明公开
    SHIFT REGISTER, DRIVE CIRCUIT AND DISPLAY SUBSTRATE 审中-公开

    公开(公告)号：EP4120229A1

    公开(公告)日：2023-01-18

    申请号：EP21929501.1

    申请日：2021-03-09

    申请人： BOE Technology Group Co., Ltd. ,  Chengdu BOE Optoelectronics Technology Co., Ltd.

    发明人： XIAO, Yunsheng ,  QING, Haigang

    IPC分类号： G09G3/20 ,  G11C19/28

    摘要： The present disclosure provides a shift register including a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a first capacitor and an impedance transistor; the first transistor has a first electrode coupled to a signal input terminal and a second electrode coupled to a first node; the second transistor has a control electrode coupled to the first node, a first electrode coupled to a second node, and a second electrode coupled to the first clock signal line; the third transistor has a first electrode coupled to a first power terminal and a second electrode coupled to the second node; the fourth transistor has a first electrode coupled to a second electrode of the fifth transistor and a second electrode coupled to the first node; the fifth transistor has a control electrode coupled to a third node and a first electrode coupled to a second power terminal; the first capacitor has a first electrode coupled to a fourth node and a second electrode coupled to the second clock signal line; the impedance transistor has a control electrode coupled to the first power terminal, a first electrode coupled to the second node, and a second electrode coupled to the third node.

    SHIFT REGISTER CIRCUIT AND METHOD FOR DRIVING SAME, AND GATE DRIVING CIRCUIT AND DISPLAY APPARATUS
    10.
    发明公开
    SHIFT REGISTER CIRCUIT AND METHOD FOR DRIVING SAME, AND GATE DRIVING CIRCUIT AND DISPLAY APPARATUS 审中-公开

    公开(公告)号：EP4068263A1

    公开(公告)日：2022-10-05

    申请号：EP21796531.8

    申请日：2021-04-22

    申请人： BOE Technology Group Co., Ltd.

    发明人： SHANG, Guangliang ,  LU, Jiangnan ,  ZHANG, Jie ,  LIU, Libin ,  SHI, Shiming ,  WANG, Dawei

    IPC分类号： G09G3/3266 ,  G11C19/28

    摘要： Disclosed is a shift register circuit (RS), comprising a denoising control sub-circuit (20) and a denoising sub-circuit (30), wherein the denoising control sub-circuit (20) is configured to generate an alternating voltage signal according to the voltage of a first voltage end (VSS) and a signal from a second clock signal end (CB1) in response to a signal from a first clock signal end (CK1), and rectify the alternating voltage signal and then output same to a first denoising control node (PD-ox), so that the voltage of the first denoising control node (PD-ox) is maintained to be a voltage that enables the denoising sub-circuit (30) to be started; and the denoising sub-circuit (30) is configured to continuously be started under the control of the voltage of the first denoising control node (PD-ox), so as to denoise a scanning signal output end (Oput).