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1603 条记录 (耗时 0.021 秒)

    ENCODING AND DECODING OF POLAR CODES WITH DISTRIBUTED CHECK BITS
    6.
    发明公开
    ENCODING AND DECODING OF POLAR CODES WITH DISTRIBUTED CHECK BITS 审中-实审

    公开(公告)号：EP4280494A3

    公开(公告)日：2024-04-17

    申请号：EP23184332.7

    申请日：2013-04-27

    申请人： Huawei Technologies Co., Ltd.

    发明人： LI, Bin ,  SHEN, Hui

    IPC分类号： H03M13/29 ,  H03M13/13 ,  H03M13/37 ,  H04L1/00 ,  H03M13/09 ,  H03M13/11

    CPC分类号： H03M13/13 ,  H03M13/3738 ,  H03M13/09 ,  H03M13/1102 ,  H03M13/2906 ,  H04L1/0054 ,  H04L1/0061 ,  H04L1/0057

    摘要： Embodiments of the present invention provide an encoding/decoding method, apparatus, and system, and relate to the communications field. The present invention may improve decoding performance and improve accuracy of a survivor path. The method includes: encoding information bits according to a first-level encoding method to obtain a first-level encoded code word, obtaining a sorting value of each check bit of the first-level encoded code word, and adjusting each check bit to a corresponding position according to the sorting value of each check bit, where the sorting value refers to a value of S when the check bit is related to first S information bits of the information bits in the first-level encoded code word, and S is a non-zero integer; and performing, according to a second-level encoding method, second-level encoding on the first-level encoded code word after positions of the check bits are adjusted, thereby obtaining a second-level encoded code word. The present invention is applicable to various communication systems.

    METHOD FOR CYCLIC CODE ENCODING, AND CHIP, CIRCUIT ASSEMBLY AND ELECTRONIC DEVICE
    10.
    发明公开
    METHOD FOR CYCLIC CODE ENCODING, AND CHIP, CIRCUIT ASSEMBLY AND ELECTRONIC DEVICE 审中-公开

    公开(公告)号：EP4311112A1

    公开(公告)日：2024-01-24

    申请号：EP22790836.5

    申请日：2022-03-31

    申请人： Huawei Technologies Co., Ltd.

    发明人： LI, Liang ,  YUAN, Chun ,  LU, Yuchun ,  MA, Lin ,  LIU, Yongzhi

    IPC分类号： H03M13/11

    摘要： According to embodiments of the present disclosure, a method and a chip for cyclic code encoding, a circuit component, and an electronic device are provided. A first cyclic code includes K payload symbols and (N-K) parity symbols, and each symbol includes m bits, where K, N, and m are integers greater than or equal to 1, and N is greater than K. The method includes: generating, based on a first symbol sequence related to a first part of symbols in the K payload symbols, a first parity sequence corresponding to the first symbol sequence. The method further includes: generating, based on a second symbol sequence related to a second part of symbols in the K payload symbols, a second parity sequence corresponding to the second symbol sequence, where the first part of symbols are different from the second part of symbols. The method further includes: generating the (N-K) parity symbols based on the first parity sequence and the second parity sequence. In this way, a small bit width cyclic code encoder may be used to implement large bit width cyclic code encoding.