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公开(公告)号：JP2004325340A
公开(公告)日：2004-11-18
申请号：JP2003122256
申请日：2003-04-25
Applicant: Toshiba Corp , 株式会社東芝
Inventor： YOSHIDA TAKASHI
IPC: G01R31/28 , G01R31/317 , G01R31/3193 , G06F11/22 , G11C11/413 , G11C29/00 , G11C29/12 , H03K19/00 , H03L7/00
CPC classification number: G01R31/31727 , G01R31/31937
Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit for easy testing. SOLUTION: The semiconductor integrated circuit comprises a plurality of split stages 2a 1 -2a 4 and 2b 1 -2b 4 where a system bus 2 for transferring signals is divided, stage elements 3a 1 -3a 3 and 3b 1 -3b 3 for connecting the split stages 2a 1 -2a 4 and 2b 1 -2b 4 in series, and a plurality of functional modules 1a-1c connected to the split stages 2a 1 -2a 4 and 2b 1 -2b 4 different from each other. The stage elements 3a 1 -3a 3 and 3b 1 -3b 3 operate in a split mode where the signal transferred from the split stages 2a 1 -2a 3 and 2b 2 -2b 4 on the input side is transferred to the split stages 2a 2 -2a 4 and 2b 1 -2b 3 on the output side in synchronism with clock signal Ck, and in a through mode where the signal transferred from the split stages 2a 1 -2a 3 and 2b 2 -2b 4 on the input side is transferred to the split stages 2a 2 -2a 4 and 2b 1 -2b 3 on the output side as required. COPYRIGHT: (C)2005,JPO&NCIPI
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62.发明专利
公开(公告)号：JP2004212310A
公开(公告)日：2004-07-29
申请号：JP2003001741
申请日：2003-01-08
Applicant: Toshiba Corp , 株式会社東芝
Inventor： TANAKA YOSHIYUKI , KOJIMA YOSHINARI
IPC: G01R31/28 , G01R31/317 , G01R31/3183 , H01L21/822 , H01L27/04
CPC classification number: G01R31/31727
Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit including an operation test circuit that apparently realizes an operation test by a clock signal of relatively high-frequency and of variably changeable frequency, by a clock signal of a relatively low-frequency for the operation test to measure the maximum normally operated frequency. SOLUTION: The clock signal is supplied to the first flip-flop 2 via a phase control circuit 4, out of the first and second flip-flop 2, 3 provided in both ends of a tested circuit 1 desired to conduct the operation test. The phase control circuit 4 is a circuit capable of controlling a phase of the clock signal variably by a test executing person, and the first and second flip-flop 2, 3 are operated nonsynchonizedly using it to realize the operation test of the apparently high-frequency. COPYRIGHT: (C)2004,JPO&NCIPI
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公开(公告)号：JP5554365B2
公开(公告)日：2014-07-23
申请号：JP2012092236
申请日：2012-04-13
Applicant: メンター グラフィックス コーポレイション
Inventor： ムルガルスキ，グジェゴシュ , ラジェスキ，ヤヌーシュ , ティスザー，イェジ , チェン，ウータン , ムケルジー，ニランジャン , カッサブ，マーク
IPC: G01R31/28 , G01R31/3183
CPC classification number: G01R31/3177 , G01R31/2851 , G01R31/31723 , G01R31/31727 , G01R31/318547 , G01R31/318563 , G01R31/318566
Abstract: Disclosed herein are exemplary embodiments of a so-called "X-press" test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compaction ratios on the order of 1000x. Exemplary embodiments of the disclosed compactor can maintain about the same coverage and about the same diagnostic resolution as that of conventional scan-based test scenarios. Some embodiments of a scan chain selection scheme can significantly reduce or entirely eliminate unknown states occurring in test responses that enter the compactor. Also disclosed herein are embodiments of on-chip comparator circuits and methods for generating control circuitry for masking selection circuits.
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64.发明专利
公开(公告)号：JP5381001B2
公开(公告)日：2014-01-08
申请号：JP2008267419
申请日：2008-10-16
Applicant: 富士通セミコンダクター株式会社
Inventor： 俊一郎 正木
IPC: G01R31/28 , H01L21/822 , H01L27/04
CPC classification number: H03C1/06 , G01R31/31727 , G06F1/08 , H03K3/84
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公开(公告)号：JP5268656B2
公开(公告)日：2013-08-21
申请号：JP2008555415
申请日：2007-02-19
Applicant: メンター グラフィックス コーポレイション
Inventor： ムルガルスキ，グジェゴシュ , ラジェスキ，ヤヌーシュ , ティスザー，イェジ , チェン，ウ−タン , ムケルジー，ニランジャン , カッサブ，マーク
IPC: G01R31/28 , G01R31/3183
CPC classification number: G01R31/3177 , G01R31/2851 , G01R31/31723 , G01R31/31727 , G01R31/318547 , G01R31/318563 , G01R31/318566
Abstract: Disclosed herein are exemplary embodiments of a so-called "X-press" test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compaction ratios on the order of 1000×. Exemplary embodiments of the disclosed compactor can maintain about the same coverage and about the same diagnostic resolution as that of conventional scan-based test scenarios. Some embodiments of a scan chain selection scheme can significantly reduce or entirely eliminate unknown states occurring in test responses that enter the compactor. Also disclosed herein are embodiments of on-chip comparator circuits and methods for generating control circuitry for masking selection circuits.
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公开(公告)号：JP5255282B2
公开(公告)日：2013-08-07
申请号：JP2007552943
申请日：2006-12-26
Applicant: 株式会社アドバンテスト
IPC: G01R31/28 , G01R31/319
CPC classification number: G01R31/31725 , G01R31/31726 , G01R31/31727 , G01R31/31937
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公开(公告)号：JP5052102B2
公开(公告)日：2012-10-17
申请号：JP2006308258
申请日：2006-11-14
Applicant: テクトロニクス・インコーポレイテッドTektronix,Inc.
Inventor： エバン・アルブライト , スコット・イー・ジンク , ダニエル・ジー・ベイカー , バリー・エイ・マックキベン , ミカエル・エス・オバートン , ミカエル・ディ・ナカムラ
CPC classification number: H04L1/205 , G01R13/0254 , G01R31/31711 , G01R31/31725 , G01R31/31727
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68.发明专利
公开(公告)号：JP4940846B2
公开(公告)日：2012-05-30
申请号：JP2006248073
申请日：2006-09-13
Applicant: 富士通セミコンダクター株式会社
IPC: H04L7/02
CPC classification number: H04L7/033 , G01R31/31725 , G01R31/31727
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公开(公告)号：JPWO2010004755A1
公开(公告)日：2011-12-22
申请号：JP2010519653
申请日：2009-07-09
Applicant: 株式会社アドバンテスト
IPC: G01R31/319 , G11C29/56
CPC classification number: H03L7/0812 , G01R31/31725 , G01R31/31727 , G01R31/31922 , G11C29/56 , G11C29/56008 , G11C29/56012 , H03L7/099
Abstract: 回路規模を小さくする試験装置、試験方法を提供する。前記被試験デバイスが出力する出力データの位相と略等しい再生クロックを生成する再生クロック生成回路は、前記被試験デバイスが出力した前記出力データの位相と前記再生クロックの位相とを比較し、位相差信号を出力する位相比較器と、前記位相差信号に基づき出力値がアップまたはダウンするバイナリカウンタと、前記バイナリカウンタの前記出力値に基づき制御信号を生成する制御信号生成部と、前記制御信号に基づき前記基準クロックの位相を移相する位相シフタとを有する。
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公开(公告)号：JP2011163842A
公开(公告)日：2011-08-25
申请号：JP2010025153
申请日：2010-02-08
Applicant: Renesas Electronics Corp , ルネサスエレクトロニクス株式会社
Inventor： SAWAI YASUNORI
IPC: G01R31/28 , H01L21/822 , H01L27/04
CPC classification number: G06F11/24 , G01R31/31726 , G01R31/31727 , G11C29/50012 , G11C29/56012
Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device which can be appropriately diagnosed and a method of diagnosing the same.
SOLUTION: This semiconductor device includes a test target circuit 19 being the object of self-diagnosis, a PLL circuit 18 outputting a clock for self-diagnosis to the target circuit 19, a register 16 for diagnosis storing a clock frequency corresponding to an operating speed limit of the target circuit 19, and a control circuit 14 for setting the frequency of the clock output from the PLL circuit 18 in self-diagnosis based on the clock frequency stored in the register 16.
COPYRIGHT: (C)2011,JPO&INPITAbstract translation: 要解决的问题：提供可以适当诊断的半导体器件及其诊断方法。 解决方案：该半导体器件包括作为自诊断对象的测试对象电路19，向目标电路19输出用于自诊断的时钟的PLL电路18，存储对应于 目标电路19的工作速度限制，以及控制电路14，用于根据存储在寄存器16中的时钟频率，自动诊断PLL电路18输出的时钟频率。
版权所有（C） ）2011，JPO＆INPIT
