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公开(公告)号：JP5338859B2
公开(公告)日：2013-11-13
申请号：JP2011141484
申请日：2011-06-27
Applicant: ソニー株式会社
Abstract: PROBLEM TO BE SOLVED: To provide a storage device capable of making a redundant write operation of unselected data unnecessary and optimizing an arrangement of pages to a state having a high efficiency for rewriting. SOLUTION: There is provided a storage device which comprises a first memory unit, a second memory unit having a different access speed from the first memory, and a control circuit. The storage device is provided with an address conversion table indicating correspondence between page addresses input from the outside and actual locations of the page data in the first or second memory unit using specific data groups as page units. The control circuit has a function to timely move the stored data in two ways between the first memory unit and the second memory unit. The control circuit is configured to move data from the first memory unit to the second memory unit in units of pages, update the address conversion table, and then invalidate the original page regions in the first memory unit, and is also configured to move data from the second memory unit to the first memory unit in units of pages, update the address table, and then invalidate the original page regions in the second memory unit. COPYRIGHT: (C)2012,JPO&INPIT
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公开(公告)号：JP4956922B2
公开(公告)日：2012-06-20
申请号：JP2005171141
申请日：2005-06-10
Applicant: ソニー株式会社
CPC classification number: G06F12/0246 , G06F3/0641 , G06F12/00 , G06F12/0223 , G06F12/08 , G06F12/0813 , G06F12/0866 , G06F12/10 , G06F12/1009 , G06F12/1081 , G06F13/28 , G06F2212/1024 , G06F2212/2022 , G06F2212/2024 , G06F2212/7201 , G11C8/08 , G11C11/22 , Y02D10/13
Abstract: A storage device (50) able to make a redundant write operation of unselected data unnecessary and able to optimize an arrangement of pages to a state having a high efficiency for rewriting, wherein the storage device (50) has a first memory unit (51), a second memory unit (52) having a different access speed from the first memory (51), and a control circuit (54), wherein the control circuit (54) has a function of timely moving the stored data in two ways between the first memory unit (51) and the second memory unit (52) having different access speeds in reading or rewriting.
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3.发明专利
公开(公告)号：JP4641702B2
公开(公告)日：2011-03-02
申请号：JP2002336016
申请日：2002-11-20
Applicant: Okiセミコンダクタ株式会社 , ソニー株式会社
IPC: H01L27/105 , H01L21/8242 , H01L21/8246 , H01L27/108
Abstract: PROBLEM TO BE SOLVED: To provide a ferroelectric nonvolatile semiconductor memory having a stacked capacitor structure and a structure wherein a contact plug is reliably prevented from being oxidized. SOLUTION: The ferroelectric nonvolatile semiconductor memory consists of a selection transistor TR, interlayer insulating layer 16, contact plug 18A, diffusion barrier layer 20, lower electrode 21, ferroelectric layer 22 and upper electrode 23. A side wall of the lower electrode 21 is covered with a first oxygen barrier layer 40, while a second oxygen barrier layer 41 is formed on a portion of the oxygen barrier layer 40, proximate to the lower end of the lower electrode 21 and the surface of the interlayer insulating layer 16. COPYRIGHT: (C)2004,JPO
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公开(公告)号：JP4062247B2
公开(公告)日：2008-03-19
申请号：JP2003413160
申请日：2003-12-11
Applicant: ソニー株式会社
CPC classification number: G11C29/4401 , G11C29/44 , G11C29/846 , G11C2029/1208
