-
公开(公告)号：JP4593088B2
公开(公告)日：2010-12-08
申请号：JP2003198259
申请日：2003-07-17
IPC分类号： H01L21/8247 , G11C11/56 , G11C16/02 , G11C16/04 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0458 , G11C2211/5612 , H01L27/115 , H01L29/7887
摘要： Disclosed is a flash memory cell and method of manufacturing the same, and programming/erasing/reading method thereof. The flash memory cell comprises a first tunnel oxide film formed at a given region of a semiconductor substrate, a first floating gate formed on the first tunnel oxide film, a second tunnel oxide film formed over the semiconductor substrate and along one sidewall of the first floating gate, a second floating g ate isolated from the first floating gate while contacting the second tunnel oxide film, a dielectric film formed on the first floating gate and the second floating gate, a control gate formed on the dielectric film, a first junction region formed in the semiconductor substrate below one side of the second tunnel oxide film, and a second junction region formed in the semiconductor substrate below one side of the first tunnel oxide film. Therefore, the present invention can implement 2-bit cell or 3-bit cell of a high density using the existing process technology. Further, it can reduce the manufacture cost and implement a high-integrated flash memory cell that is advantageous than a conventional flash memory cell in view of charge storage/retention as well as programming time.
-
公开(公告)号：JP3806402B2
公开(公告)日：2006-08-09
申请号：JP2002353409
申请日：2002-12-05
IPC分类号： G11C16/06 , G11C11/56 , G11C16/02 , G11C16/04 , G11C16/28 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/28 , G11C11/5642
摘要： The present invention relates to a sensing circuit in a multi-level flash memory cell capable of exactly sensing a state of the multi-level flash memory cell by sensing four states of the multi-level flash memory cell based on first through third reference cells. The first reference cell has a threshold voltage by which a program or erase state of a floating gate can be determined in a state that a capacitor of the multi-level flash memory cell is discharged, a second reference cell has a threshold voltage by which a charge or discharge state of the capacitor can be determined with the floating gate of the multi-level flash memory cell being at a discharge state, and a third reference cell has a threshold voltage by which a charge or discharge state of the capacitor can be determined with the floating gate of the multi-level flash memory cell being at a program state.
-
搜索结果
2 条记录 (耗时 0.019 秒)
