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公开(公告)号：JPH0328955A
公开(公告)日：1991-02-07
申请号：JP16296189
申请日：1989-06-26
Applicant: TOSHIBA CORP
Inventor： NOGUCHI TOSHIHIKO
IPC: G06F15/16
Abstract: PURPOSE:To simplify the entire constitution of a data processor and to improve the extension properties of an auxiliary control means by using a 2nd storage means to perform the transfer of data between a main control means and the auxiliary control means. CONSTITUTION:A main control means 11 stores the auxiliary data into a proper address of a 2nd storage means 18 of an auxiliary control means 16 at execution of the auxiliary control and at the same time stores the address data showing the proper address into a specified address. Then the means 16 computes the auxiliary control data based on the auxiliary data stored in a proper address shown by the address data stored in the specified address of the means 18 and at the same time stores the computed data in the proper address when the address data stored in the specific address is proper to the means 16 itself. As a result, the means 11 controls a control subject based on the auxiliary control data stored in the proper address of the means 18. Thus the entire constitution of a data processor is simplified and at the same time the extension properties of the means 16 connected to the means 11 can be improved.
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公开(公告)号：JPH0291515A
公开(公告)日：1990-03-30
申请号：JP24229888
申请日：1988-09-29
Applicant: TOSHIBA CORP
Inventor： NOGUCHI TOSHIHIKO
Abstract: PURPOSE:To convert the angle of rotation of a resolver into a digital signal by operating the difference between the outputs of 1st and 2nd multiplication type D/A converters and outputting it as the control input of a voltage- controlled oscillation means. CONSTITUTION:The rotor winding 10c of the two-phase excited and one-phase output resolver 10 is connected to the analog reference input of a multiplication type D/A converter 2a constituting a multiplying means 2 and its output is connected to the uninvested input (+) of a subtracting means 4 consisting of resistances 4a - 4d and an operational amplifier 4e. The output of a sin2theta/2- function generating means 11 consisting of a ROM 11a, a multiplication type D/A converter 11b, and a variable resistance 11c, on the other hand, is connected to the inverted input (-) of the subtracting means 4. The voltage-controlled oscillation means 5 oscillates by receiving an error output which is the output of the subtracting means 4 to output a pulse train to a counting means 6, which outputs a digital signal; and a costheta-function generating means 7 and the sin2theta/2- function generating means 11 send their outputs to the multiplying means 2 and subtracting means 4 respectively. Consequently, the angle thetam of rotation of the resolver 10 is accurately converted into the digital signal.
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公开(公告)号：JPS6373882A
公开(公告)日：1988-04-04
申请号：JP21266686
申请日：1986-09-11
Applicant: TOSHIBA CORP
Inventor： NOGUCHI TOSHIHIKO
IPC: H02M7/48
Abstract: PURPOSE:To keep well-balanced current control for each phase, by getting an inverter to have a pulse width modulation to each phase, and by turning ON switching elements for each phase one after another in every definite time on the basis of this comparison output. CONSTITUTION:A signal generating circuit 8 generates a clock pulse Pc and gives it to pulse width modulation circuits 9a-9c for each phase. These pulse width modulation circuits 9a-9c give switching signals to transistors Tr 1-Tr 6 for each phase in an inverter main circuit 2 and is composed of a comparison means 10 made up of a subtraction circuit 10a and a comparison circuit 10b, an edge detection circuit 11 as an output change detection means, a counter 12 comprising a digital type timer means, and a D flip flop 13. With the output signals from the output terminal of this D flip flop 13, transistors Tr 1-Tr 6 for each phase are turned ON and OFF respectively. In this way, there will be no unbalance in timer operating time in each phase or not possibility of fluctuation which might be caused by the ambient temperature, etc.
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公开(公告)号：JPS62173995A
公开(公告)日：1987-07-30
申请号：JP1657786
申请日：1986-01-27
Applicant: TOSHIBA CORP
Inventor： NOGUCHI TOSHIHIKO , TAKAHASHI ISAO
Abstract: PURPOSE:To make it possible to perform the flux operation accurate in all rotary regions and strong against the constant fluctuations by forming a flux operation circuit with a high-speed system operation means and a low-speed system operation means. CONSTITUTION:When an induction motor 2 is rotating on high speed, outputs Ppsi1qTc and Ppsi1dTc of operational amplifiers 9a and 9b become greater than the outputs psi1q and psi1d of operational amplifiers 21a and 21b, while the operation of flux elements which is based on the integration is performed because the primary lag active filters 10a and 10b actuate as integrators. Conversely, when the induction motor 2 is rotating on low speed, the output psi1q and psi1d of operational amplifiers 21a and 21b become greater than the outputs of operational amplifiers 9a and 9b, while the filters 10a and 10b actuate as transfer function 1; so that the operation of the flux elements which is based on the rotary coordination conversion is performed.
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公开(公告)号：JPS62173950A
公开(公告)日：1987-07-30
申请号：JP1659986
申请日：1986-01-28
Applicant: TOSHIBA CORP
Inventor： NOGUCHI TOSHIHIKO
Abstract: PURPOSE:To permit measurement of instantaneous torque in a mechanically non-contact manner and over a total speed range by measuring an instantaneous torque from an instantaneous value of primary current and an rotation angle of a rotor. CONSTITUTION:If a three-phase squirrel-cage induction motor 2 is driven by a power source 1, a pulse of frequency proportional to a rotational speed from an incremental type rotary encoder 3 is sent to a counter 4. ROMs 5a, 5b are read out by an output power of the counter 4, which output power becomes an input of multiplying D/A converters 6a-6d The detection output of a primary current instantaneous value from halls CT7a, 7b is also given to these converters 6a-6d. The output power of converters 6a-6d are successively given to operational amplifier 9a, 9b, active filters 10a, 10b, multipliers 11a, 11b and an operational amplifier 12 so that an output power indicating an instantaneous torque will be derived.
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公开(公告)号：JPH04331489A
公开(公告)日：1992-11-19
申请号：JP9937191
申请日：1991-05-01
Applicant: TOSHIBA CORP
Inventor： NOGUCHI TOSHIHIKO
IPC: H02P1/52 , H02P6/06 , H02P6/08 , H02P6/10 , H02P6/20 , H02P21/05 , H02P23/04 , H02P25/026 , H02P27/06
Abstract: PURPOSE:To make the stepped interval of phase command as short as possible and to obtain a sine wave output current from an inverter as quick as possible. CONSTITUTION:Upon turn ON of power, an absolute position detecting means 15 produces a rough phase command at first. At a time point when the detection output of the absolute position detecting means 15 makes an initial variation, a relative position detecting means 16 outputs a correct phase command. Consequently, output current of an inverter 23 immediately becomes sinusoidal for each phase resulting in suppression of ripple and the like.
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公开(公告)号：JPS63282892A
公开(公告)日：1988-11-18
申请号：JP11798187
申请日：1987-05-14
Applicant: TOSHIBA CORP
Inventor： NOGUCHI TOSHIHIKO
Abstract: PURPOSE:To more accurately execute the binarization conversion of a bar code by cutting the leading edge part of a binarization signal corresponding to an initial bar by a prescribed time by means of an outputting means at the time of detecting the binarization signal and then outputting the cut binarization signal as it is. CONSTITUTION:When the binarization signal corresponding to the initial bar of a bar code out of binarization signals outputted from a binarization signal generating means at the time of scanning the bar code is detected by a detecting means 6, the leading edge part of the binarization signal corresponding to the initial bar is cut by the prescribed time by an output means 10 and the cut signal is outputted. Thereby, the comparatively advanced output timing of the binarization signal corresponding to the initial bar is delayed. The binarization signals successively outputted are outputted by an output means 10 without changing the output timing. The slight advancement of the output timing of the binarization signal corresponding to the initial bar at the time of increasing resolution is corrected and the binarization conversion of the bar code can be more accurately executed.
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公开(公告)号：JPS6352519A
公开(公告)日：1988-03-05
申请号：JP19669586
申请日：1986-08-22
Applicant: TOSHIBA CORP
Inventor： TAKEUCHI FUMIAKI , NOGUCHI TOSHIHIKO
IPC: H03M1/36
Abstract: PURPOSE:To detect a peak minutely with a less phase deviation by using the principle that the time required for the change by a prescribed potential difference V is transferred from the decreasing state into the increasing state before aud after the inflection point of an analog signal waveform peak value so as to detect the passing of the inflection point thereby inverting the logical output. CONSTITUTION:A comparison means 31 consists of comparators 11-17, a reference voltage generating circuit 18, leading edge detection circuits 11a-17a, trailing edge detection circuits 11b-17b and OR circuits 29, 30, and a detection pulse 1 is outputted from the circuit 29 at the point of time when an analog signal (v) crosses reference voltages Vref1-Vref7 from the low potential toward the high potential and from a circuit 30 at the time when the signal crosses the voltages from the high toward the low potentials. A count means 32 cosists of an OR circuit 33, a clock pulse generating circuit 34 and a counter 35 and measures a difference time between cross point of times sequentially. A coding means 36 consists of an RS flip-flop 37 and a microcomputer 38, compares the quantities of the adjacent difference times before and after each difference time among the difference times and inverts the logical output when a difference time tends to be increasing from the decreasing state.
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公开(公告)号：JPS6268321A
公开(公告)日：1987-03-28
申请号：JP20807285
申请日：1985-09-20
Applicant: TOSHIBA CORP
Inventor： NOGUCHI TOSHIHIKO
Abstract: PURPOSE:To minimize the deviation of the phase for an analog signal and a digital signal while attaining digitization to a minute peak by changing the logic value of the digital signal based on the change in the ruggedness of a waveform of the analog signal. CONSTITUTION:The analog signal is inputted to the 1st-3rd sample-and-hold circuits 2-4 equivalent to storage means via a filter 1 and an astable multivibrator 5 outputs a clock pulse to a timing pulse generation circuit 6. A prescribed sampling frequency control signal is given to the sample-and-hold circuits 2-4 from the timing pulse generating circuit 6 respectively. An operation means 7 consists of the combination of the 1st-6th analog switches 8-13, the 1st and 2nd adder circuits 14, 15 and an attenuator 16. An inverting input (-) of a comparator 17 equivalent to the comparison means is connected to the output of the attenuator 16, a non-inverting input (+) is connected to an output of the 2nd adder circuit 15 and the output terminal is connected to a data terminal D of a D flip-flop 18.
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公开(公告)号：JPH04316208A
公开(公告)日：1992-11-06
申请号：JP11096291
申请日：1991-04-15
Applicant: TOSHIBA CORP
Inventor： NOGUCHI TOSHIHIKO
IPC: H03H17/02
Abstract: PURPOSE:To cancel the lack of outputs caused by quantization omitting error caused by digital arithmetic. CONSTITUTION:An adder 12 calculates and outputs error n between an input Xn at a sample point (n) and a preceding output Yn-1 stored in a primary delay memory 19 at a sample point (n-1). An error operating means 16 is equipped with gains G1 (0
