公开(公告)号：US08466624B2

公开(公告)日：2013-06-18

申请号：US12553688

申请日：2009-09-03

申请人： Nels Jewell-Larsen ,  Kenneth A. Honer ,  Matt Schwiebert ,  Hongyu Ran ,  Piyush Savalia ,  Yan Zhang

发明人： Nels Jewell-Larsen ,  Kenneth A. Honer ,  Matt Schwiebert ,  Hongyu Ran ,  Piyush Savalia ,  Yan Zhang

IPC分类号： H05B31/26

CPC分类号： F28F13/16 ,  F28D15/02 ,  F28F2250/08 ,  H02N11/006

摘要： Performance of an electrohydrodynamic fluid accelerator device may be improved and adverse events such as sparking or arcing may be reduced based, amongst other things, on electrode geometries and/or positional interrelationships of the electrodes. For example, in a class of EHD devices that employ a longitudinally elongated corona discharge electrode (often, but not necessarily, a wire), a plurality of generally planar, collector electrodes may be positioned so as to present respective leading surfaces toward the corona discharge electrode. The generally planar collector electrodes may be oriented so that their major surfaces are generally orthogonal to the longitudinal extent of the corona discharge electrode. In such EHD devices, a high intensity electric field can be established in the “gap” between the corona discharge electrode and leading surfaces of the collector electrodes.

摘要翻译： 电子流体动力学流体加速器装置的性能可以被改善，并且可以基于电极的电极几何形状和/或位置相互关系来减少不利的事件，例如火花或电弧。 例如，在采用纵向长度电晕放电电极（通常但不一定是导线）的一类EHD装置中，可以将多个大体上平面的集电极定位成使得各自的前表面朝向电晕放电 电极。 大致平面的集电极可以被定向成使得它们的主表面大致垂直于电晕放电电极的纵向延伸。 在这样的EHD装置中，可以在电晕放电电极和集电极的前表面之间的“间隙”中建立高强度电场。

公开(公告)号：US08392777B2

公开(公告)日：2013-03-05

申请号：US12549164

申请日：2009-08-27

申请人： Wei-Yu Chen ,  Kevin B. Badgett ,  Siegfried Kay Hesse ,  Timothy J. Wood

发明人： Wei-Yu Chen ,  Kevin B. Badgett ,  Siegfried Kay Hesse ,  Timothy J. Wood

IPC分类号： G01R31/28

CPC分类号： G11C29/44 ,  G11C29/4401 ,  G11C2029/0401 ,  G11C2029/1208 ,  G11C2029/4402

摘要： Failure and repair information collected during self-testing of arrays in an integrated circuit is stored in a centralized array in the integrated circuit. In that way, a centralized array can be read out to provide failure and repair information on the arrays in the integrated circuit rather than having to read from each array. In addition, the failure and repair information may also be stored in the array under test for certain of the arrays.

摘要翻译： 在集成电路中的阵列自检期间收集的故障和修复信息存储在集成电路中的集中式阵列中。 以这种方式，可以读取集中式阵列，以提供集成电路中阵列的故障和修复信息，而不必从每个阵列读取。 此外，故障和修复信息也可能存储在被测阵列中的某些阵列中。

公开(公告)号：US08386747B2

公开(公告)日：2013-02-26

申请号：US12483051

申请日：2009-06-11

申请人： William C. Moyer ,  James B. Eifert

发明人： William C. Moyer ,  James B. Eifert

IPC分类号： G06F13/00 ,  G06F13/28 ,  G06F9/46 ,  G06F9/00 ,  G11C8/00

CPC分类号： G06F12/1036 ,  G06F12/0284 ,  G06F12/109

摘要： Non-intrusive techniques have been developed to dynamically and selectively alter address translations performed by, or for, a processor. For example, in some embodiments, a memory management unit is configured to map from effective addresses in respective effective (or virtual) address spaces to physical addresses in the memory, wherein the mappings performed by the memory management unit are based on address translation entries of an address translation table. For a subset of less than all processes, entry selection logic selects from amongst plural alternative mappings coded in respective ones of the address translation entries. For at least some effective addresses mapped for a particular process of the subset, selection of a particular address translation entry is based on an externally sourced value. In some embodiments, only a subset of effective addresses mapped for the particular process are subject to dynamic runtime alteration of the address translation entry selection.

摘要翻译： 已经开发了非侵入性技术来动态地和选择性地改变由处理器执行的或为处理器执行的地址转换。 例如，在一些实施例中，存储器管理单元被配置为将相应的有效（或虚拟）地址空间中的有效地址映射到存储器中的物理地址，其中由存储器管理单元执行的映射基于地址转换条目 地址转换表。 对于少于所有进程的子集，条目选择逻辑从在各个地址转换条目中编码的多个备选映射中进行选择。 对于为子集的特定过程映射的至少一些有效地址，特定地址转换条目的选择基于外部来源的值。 在一些实施例中，仅为特定进程映射的有效地址的子集经受地址转换条目选择的动态运行时间更改。

公开(公告)号：US08374016B2

公开(公告)日：2013-02-12

申请号：US13069853

申请日：2011-03-23

申请人： Jeffrey A. Correll

发明人： Jeffrey A. Correll

IPC分类号： G11C17/00

CPC分类号： G11C17/16 ,  G11C17/12

摘要： An apparatus includes a bit cell of a programmable memory circuit. The bit cell includes a programmable device. The bit cell includes a first device having a first type. The first device is configured to conduct a first current between a first node and a second node in response to a first value of a signal on the word line and a signal on a bit line. The programmable device is configured to be programmed in response to a first level of the first current. The bit cell includes a circuit coupled to the second node. The circuit is configured to reduce a leakage current through the first device in response to a second value of the signal on the word line and based on a feedback signal. In at least one embodiment of the apparatus, the feedback signal is based on a signal on the bit line.

摘要翻译： 一种装置包括可编程存储器电路的位单元。 位单元包括可编程器件。 位单元包括具有第一类型的第一器件。 第一设备被配置为响应于字线上的信号的第一值和位线上的信号在第一节点和第二节点之间传导第一电流。 可编程设备被配置为响应于第一电流的第一电平被编程。 比特单元包括耦合到第二节点的电路。 电路被配置为响应于字线上的信号的第二值并且基于反馈信号来减少通过第一器件的漏电流。 在装置的至少一个实施例中，反馈信号基于位线上的信号。

公开(公告)号：US08358632B2

公开(公告)日：2013-01-22

申请号：US12648017

申请日：2009-12-28

申请人： Kevin M. Boyd ,  Salvador Garcia, Jr. ,  Eamonn Gormley ,  Anh Nguyen

发明人： Kevin M. Boyd ,  Salvador Garcia, Jr. ,  Eamonn Gormley ,  Anh Nguyen

IPC分类号： H04J3/00

CPC分类号： H04W74/085

摘要： A method for accessing a reverse channel for communication from a remote unit to a base station is disclosed. The method includes waiting a random period of time in response to determining that the reverse channel is available at a first time. The method also includes monitoring a forward channel after expiration of the random period of time to determine whether the reverse channel is available at a second time. The method further includes transmitting a first portion of data on the reverse channel in response to determining that the reverse channel is available at the second time.

摘要翻译： 公开了一种用于访问用于从远程单元到基站的通信的反向信道的方法。 所述方法包括响应于确定所述反向信道在第一时间可用而等待随机时间段。 该方法还包括在随机时间段到期之后监视前向信道，以确定反向信道是否在第二时间可用。 该方法还包括响应于确定反向信道在第二时间可用而在反向信道上发送数据的第一部分。

公开(公告)号：US08356130B2

公开(公告)日：2013-01-15

申请号：US12633032

申请日：2009-12-08

申请人： Karin Strauss ,  Jaewoong Chung

发明人： Karin Strauss ,  Jaewoong Chung

IPC分类号： G06F13/24

CPC分类号： G06F13/26 ,  G06F9/4818 ,  G06F13/4022

摘要： A method includes recording a user-level interrupt as undeliverable in a mailbox at least partially based on an interrupt domain identifier and an interrupt recipient identifier included in a user-level interrupt message associated with the user-level interrupt. The recording is at least partially based on an indication that the user-level interrupt is undeliverable to a recipient application thread executing on a processor core of a plurality of processor cores in a multi-core system.

摘要翻译： 一种方法包括至少部分地基于包含在与用户级别中断相关联的用户级中断消息中的中断域标识符和中断接收者标识符，在邮箱中记录无法投递的用户级中断。 该记录至少部分地基于在多核系统中的多个处理器核的处理器核上执行的接收应用程序线程的用户级别中断不可投递的指示。

公开(公告)号：US08349635B1

公开(公告)日：2013-01-08

申请号：US12124043

申请日：2008-05-20

申请人： Qing Gan ,  Emmanuel P. Quevy

发明人： Qing Gan ,  Emmanuel P. Quevy

IPC分类号： H01L29/84

CPC分类号： G01L9/0019 ,  B81B7/0038 ,  B81B7/0064 ,  G01C19/5783 ,  G01P2015/088

摘要： An encapsulated MEMS device and a method to form an encapsulated MEMS device are described. An apparatus includes a first substrate having a silicon-germanium seal ring disposed thereon and a second substrate having a metal seal ring disposed thereon. The metal seal ring is aligned with and bonded to the silicon-germanium seal ring to provide a sealed cavity. A MEMS device is housed in the sealed cavity. A method includes forming a silicon-germanium seal ring on a first substrate and forming a metal seal ring on a second substrate. The metal seal ring is bonded to the silicon-germanium seal ring to provide a sealed cavity that houses a MEMS device.

摘要翻译： 描述了封装的MEMS器件和形成封装的MEMS器件的方法。 一种装置包括：第一基板，其上设置有硅锗密封环;第二基板，其上设置有金属密封环。 金属密封环与硅 - 锗密封环对准并结合，以提供密封腔。 MEMS器件容纳在密封腔中。 一种方法包括在第一基板上形成硅 - 锗密封环并在第二基板上形成金属密封环。 金属密封环被结合到硅 - 锗密封环上以提供容纳MEMS器件的密封腔。

公开(公告)号：US08327137B1

公开(公告)日：2012-12-04

申请号：US11324145

申请日：2005-12-30

申请人： Paul Erb ,  Geoffrey Strongin

发明人： Paul Erb ,  Geoffrey Strongin

IPC分类号： H04L29/06

CPC分类号： G06F21/53 ,  G06F21/85 ,  H04L63/1466

摘要： A virtualized computer system includes at least one guest environment (guest), a service guest environment (SG) and trusted software. The at least one guest includes at least one driver having a first private message interface. The SG includes a first USB host controller (HC) driver, which is in communication with a USB HC. The first USB HC driver includes a second private message interface. The trusted software is in communication with the guest and the SG. The trusted software includes a data intercept/routing mechanism that facilitates secure communication between at least one USB device coupled to the USB HC and the guest using the first and second private message interfaces.

摘要翻译： 虚拟化计算机系统包括至少一个客体环境（客人），服务访客环境（SG）和可信软件。 所述至少一个客户端包括具有第一私人消息接口的至少一个驱动器。 SG包括与USB HC通信的第一USB主机控制器（HC）驱动器。 第一个USB HC驱动程序包括第二个专用消息接口。 受信任的软件与客人和SG进行通信。 可信软件包括数据拦截/路由机制，其利用第一和第二专用消息接口促进耦合到USB HC和访客的至少一个USB设备之间的安全通信。

公开(公告)号：US08279704B2

公开(公告)日：2012-10-02

申请号：US12895523

申请日：2010-09-30

申请人： Roy E. Scheuerlein ,  Luca G. Fasoli

发明人： Roy E. Scheuerlein ,  Luca G. Fasoli

IPC分类号： G11C8/00

CPC分类号： G11C7/18 ,  G11C7/1048 ,  G11C8/08 ,  G11C8/12 ,  G11C8/14

摘要： Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks.

摘要翻译： 描述了用于解码可编程的示例性存储器阵列的电路和方法，在一些实施例中，可重写无源元件存储器单元，其对于具有多于一个存储器平面的非常密集的三维存储器阵列特别有用。 此外，描述了用于选择这种存储器阵列的一个或多个阵列块的电路和方法，用于选择所选择的阵列块内的一个或多个字线和位线，用于将数据信息传送到选定的阵列块内的选定的存储器单元 并且用于将未选择的偏置条件传送到未选择的阵列块。

公开(公告)号：US08266389B2

公开(公告)日：2012-09-11

申请号：US12431874

申请日：2009-04-29

申请人： Guhan Krishnan ,  Antonio Asaro ,  Don Cherepacha ,  Thomas R. Kunjan ,  Joerg Winkler ,  Ralf Flemming ,  Maurice B. Steinman ,  Jonathan Owen ,  John Kalamatianos

发明人： Guhan Krishnan ,  Antonio Asaro ,  Don Cherepacha ,  Thomas R. Kunjan ,  Joerg Winkler ,  Ralf Flemming ,  Maurice B. Steinman ,  Jonathan Owen ,  John Kalamatianos

IPC分类号： G06F13/18

CPC分类号： G06F13/161

摘要： A hierarchical memory request stream arbitration technique merges coherent memory request streams from multiple memory request sources and arbitrates the merged coherent memory request stream with requests from a non-coherent memory request stream. In at least one embodiment of the invention, a method of generating a merged memory request stream from a plurality of memory request streams includes merging coherent memory requests into a first serial memory request stream. The method includes selecting, by a memory controller circuit, a memory request for placement in the merged memory request stream from at least the first serial memory request stream and a merged non-coherent request stream. The merged non-coherent memory request stream is at least partially based on an indicator of a previous memory request selected for placement in the merged memory request stream.

摘要翻译： 分级存储器请求流仲裁技术将来自多个存储器请求源的相干存储器请求流合并，并且根据来自非相干存储器请求流的请求对合并的相干存储器请求流进行仲裁。 在本发明的至少一个实施例中，从多个存储器请求流生成合并存储器请求流的方法包括将相干存储器请求合并到第一串行存储器请求流中。 该方法包括由存储器控制器电路从至少第一串行存储器请求流和合并的非相干请求流中选择存储器请求，以供放置在合并的存储器请求流中。 合并的非相干存储器请求流至少部分地基于选择用于放置在合并的存储器请求流中的先前存储器请求的指示符。