利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

57 条记录 (耗时 0.03 秒)

    Methods of forming multi-level cell of semiconductor memory
    4.
    发明授权
    Methods of forming multi-level cell of semiconductor memory 有权
    形成半导体存储器多级单元的方法

    公开(公告)号：US08187918B2

    公开(公告)日：2012-05-29

    申请号：US12587772

    申请日：2009-10-13

    申请人： Gyu-Hwan Oh ,  Hyeung-Geun An ,  Soon-Oh Park ,  Dong-Ho Ahn ,  Young-Lim Park

    发明人： Gyu-Hwan Oh ,  Hyeung-Geun An ,  Soon-Oh Park ,  Dong-Ho Ahn ,  Young-Lim Park

    IPC分类号： H01L21/06

    CPC分类号： H01L45/141 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/144 ,  H01L45/1666 ,  H01L45/1683

    摘要： Provided is a method of forming a semiconductor memory cell in which in order to store two bits or more data in a memory cell, three or more bottom electrode contacts (BECs) and phase-change materials (GST) have a parallel structure on a single contact plug (CP) and set resistances are changed depending on thicknesses (S), lengths (L) or resistivities (ρ) of the three or more bottom electrode contacts, so that a reset resistance and three different set resistances enable data other than in set and reset states to be stored. Also, a method of forming a memory cell in which three or more phase-change materials (GST) have a parallel structure on a single bottom electrode contact, and the phase-change materials have different set resistances depending on composition ratio or type, so that four or more different resistances can be implemented is provided.

    摘要翻译： 提供了一种形成半导体存储单元的方法，其中为了在存储单元中存储两个或更多个数据，三个或更多个底部电极触点（BEC）和相变材料（GST）在单个存储单元上具有并联结构 接触插头（CP）和设定电阻根据三个或更多个底部电极触点的厚度（S），长度（L）或电阻率（＆rgr）而改变，因此复位电阻和三种不同的设定电阻使数据不能 在设置和复位状态下存储。 此外，形成其中三个或更多个相变材料（GST）在单个底部电极接触上具有平行结构的存储单元的方法，并且相变材料根据组成比或类型具有不同的设定电阻，因此 可以实现四个或更多个不同的电阻。

    Memory device including phase-changeable material region and method of fabricating the same
    7.
    发明授权
    Memory device including phase-changeable material region and method of fabricating the same 有权
    包括相变材料区域的存储器件及其制造方法

    公开(公告)号：US07759668B2

    公开(公告)日：2010-07-20

    申请号：US11844534

    申请日：2007-08-24

    申请人： Dong-Ho Ahn

    发明人： Dong-Ho Ahn

    IPC分类号： H01L29/04

    CPC分类号： H01L45/06 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1683 ,  Y10S977/832 ,  Y10S977/943

    摘要： A memory device includes first and second electrodes and a phase-changeable material region disposed between the first and second electrodes and including first and second portions contacting respective ones of the first and second electrodes and a third portion interconnecting the first and second portions and configured to preferentially heat with respect to the first and second portions responsive to a current passing between the first and second electrodes. The first and second portions of the phase-changeable material region may contact respective ones of the first and second electrodes at respective first and second electrode contact surfaces and the third portion may have a cross-sectional area that is less than areas of each of the first and second contact surfaces. For example, the third portion may include a filament portion extending between the first and second portions.

    摘要翻译： 存储器件包括第一和第二电极以及设置在第一和第二电极之间的相变材料区域，并且包括接触第一和第二电极中的相应电极的第一和第二部分以及互连第一和第二部分的第三部分， 响应于在第一和第二电极之间通过的电流，相对于第一和第二部分优先加热。 可相变材料区域的第一和第二部分可以在相应的第一和第二电极接触表面处接触第一和第二电极中的相应的部分，并且第三部分可以具有小于 第一和第二接触表面。 例如，第三部分可以包括在第一和第二部分之间延伸的细丝部分。

    METHODS OF FORMING CONTACT STRUCTURES AND SEMICONDUCTOR DEVICES FABRICATED USING CONTACT STRUCTURES
    8.
    发明申请
    METHODS OF FORMING CONTACT STRUCTURES AND SEMICONDUCTOR DEVICES FABRICATED USING CONTACT STRUCTURES 有权
    形成接触结构的方法和使用接触结构织造的半导体器件

    公开(公告)号：US20100144138A1

    公开(公告)日：2010-06-10

    申请号：US12627810

    申请日：2009-11-30

    申请人： Young-Lim Park ,  Hyeong-Geun An ,  Gyu-Hwan Oh ,  Dong-Ho Ahn ,  Jin-Il Lee

    发明人： Young-Lim Park ,  Hyeong-Geun An ,  Gyu-Hwan Oh ,  Dong-Ho Ahn ,  Jin-Il Lee

    IPC分类号： H01L21/768

    CPC分类号： H01L21/76816 ,  H01L27/24

    摘要： Provided are methods of forming contact structures and semiconductor devices fabricated using the contact structures. The formation of a contact structure can include forming a first molding pattern on a substrate, forming an insulating layer to cover at least a sidewall of the first molding pattern, forming a second molding pattern to cover a sidewall of the insulating layer and spaced apart from the first molding pattern, removing a portion of the insulating layer between the first and second molding patterns to form a hole, and forming an insulating pattern between the first and second molding patterns, and forming a contact pattern in the hole.

    摘要翻译： 提供了形成使用接触结构制造的接触结构和半导体器件的方法。 接触结构的形成可以包括在基底上形成第一模制图案，形成绝缘层以覆盖至少第一模制图案的侧壁，形成第二模制图案以覆盖绝缘层的侧壁并与 第一模制图案，去除第一和第二模制图案之间的绝缘层的一部分以形成孔，并且在第一和第二模制图案之间形成绝缘图案，并在孔中形成接触图案。

    Anti-lock brake system pump housing
    9.
    发明授权
    Anti-lock brake system pump housing 失效
    防抱死制动系统泵壳

    公开(公告)号：US06971858B2

    公开(公告)日：2005-12-06

    申请号：US10322418

    申请日：2002-12-19

    申请人： Dong-Ho Ahn

    发明人： Dong-Ho Ahn

    IPC分类号： B60T8/48 ,  B60T8/36 ,  F04B1/053 ,  F04B53/16 ,  F04B1/04 ,  F04B17/00

    CPC分类号： B60T8/368 ,  F04B1/053 ,  F04B53/16 ,  Y10T137/87885

    摘要： The present invention relates to an ABS pump housing. The ABS pump housing includes: a motor-receiving unit, a pump-receiving unit, an entrance solenoid valve, an exit solenoid valve and an accumulator-receiving unit, wherein the accumulator-receiving unit comprises: a first chamber, a second chamber arranged above the first chamber and having a diameter smaller than that of the first chamber, a first communication port for communicating the first chamber with the pump-receiving unit and a second communication port for communicating the second chamber with an exit solenoid valve-receiving unit in a rear end of the pump housing. A flow path of the first communication port communicating with the pump-receiving unit is readily formed in a large size. The second chamber is formed to communicate with the exit solenoid valve in the exit side so that any additional communication port is not necessary, by which the pump housing is downsized and light-weighted.

    摘要翻译： ABS泵壳体技术领域本发明涉及ABS泵壳体。 ABS泵壳体包括：电动机接收单元，泵接收单元，入口电磁阀，出口电磁阀和蓄电池接收单元，其中蓄电池接收单元包括：第一室，布置在第二室中的第二室 在第一室的上方并且具有比第一室的直径小的直径，用于使第一室与泵接收单元连通的第一连通口和用于使第二室与出口电磁阀接收单元连通的第二连通口 泵壳的后端。 与泵接收单元连通的第一通信端口的流路容易地形成为大尺寸。 第二室被形成为与出口侧的出口电磁阀连通，使得不需要任何附加的连通端口，由此泵壳体被小型化和轻量化。

    Trench isolation regions having recess-inhibiting layers therein that protect against overetching
    10.
    发明授权
    Trench isolation regions having recess-inhibiting layers therein that protect against overetching 失效
    沟槽隔离区域在其中具有防止过蚀刻的凹陷抑制层

    公开(公告)号：US06717231B2

    公开(公告)日：2004-04-06

    申请号：US10224017

    申请日：2002-08-20

    申请人： Sung-eui Kim ,  Keum-joo Lee ,  In-seak Hwang ,  Young-sun Koh ,  Dong-ho Ahn ,  Moon-han Park ,  Tai-su Park

    发明人： Sung-eui Kim ,  Keum-joo Lee ,  In-seak Hwang ,  Young-sun Koh ,  Dong-ho Ahn ,  Moon-han Park ,  Tai-su Park

    IPC分类号： H01L2176

    CPC分类号： H01L21/76224

    摘要： Methods of forming trench isolation regions include the steps of forming a semiconductor substrate having a trench therein and a masking layer thereon extending adjacent the trench. The masking layer may comprise silicon nitride. A recess-inhibiting layer is then formed on a sidewall of the trench and on a sidewall of the masking layer. Next, a stress-relief layer is formed on the recess-inhibiting layer. This stress-relief layer extends opposite the sidewall of the trench and opposite the sidewall of the masking layer and may comprise silicon nitride. The trench is then filled with a trench isolation layer. A sequence of planarization or etch-back steps are then performed to remove the masking layer and also align an upper surface of the trench isolation layer with a surface of the substrate. At least a portion of the masking layer is removed using a first etchant (e.g., phosphoric acid) that selectively etches the masking layer and the stress-relief layer at faster rates than the first recess-inhibiting layer. The recess-inhibiting layer is formed directly on a sidewall of the masking layer in order to limit the extent to which the outer surfaces of the stress-relief layer are exposed to the first etchant. In this manner, recession of the stress-relief layer and the voids that may subsequently develop as a result of the recession can be reduced. Multiple thin stress-relief layers may also be provided and these multiple layers provide a degree of stress-relief that is comparable with a single much thicker stress-relief layer.

    摘要翻译： 形成沟槽隔离区域的方法包括以下步骤：在其中形成具有沟槽的半导体衬底和其上邻近沟槽延伸的掩模层。 掩模层可以包括氮化硅。 然后在沟槽的侧壁和掩模层的侧壁上形成凹陷抑制层。 接下来，在凹陷抑制层上形成应力消除层。 该应力消除层与沟槽的侧壁相对并且与掩模层的侧壁相对延伸并且可以包括氮化硅。 然后用沟槽隔离层填充沟槽。 然后执行一系列平面化或蚀刻步骤以去除掩模层，并且还使沟槽隔离层的上表面与衬底的表面对准。 使用第一蚀刻剂（例如磷酸）去除掩模层的至少一部分，其以比第一凹陷抑制层更快的速率选择性地蚀刻掩模层和应力消除层。 凹陷抑制层直接形成在掩模层的侧壁上，以限制应力消除层的外表面暴露于第一蚀刻剂的程度。 以这种方式，可以减少应力消除层的凹陷和随后可能由于凹陷而形成的空隙。 还可以提供多个薄的应力消除层，并且这些多层提供与单个更厚的应力消除层相当的应力消除程度。