-
公开(公告)号：US20110182131A1
公开(公告)日：2011-07-28
申请号：US13080114
申请日：2011-04-05
Applicant: Mihoko Akiyama , Futoshi Igaue , Kenji Yoshinaga , Masashi Matsumura , Fukashi Morishita
Inventor： Mihoko Akiyama , Futoshi Igaue , Kenji Yoshinaga , Masashi Matsumura , Fukashi Morishita
IPC: G11C5/14
Abstract: A semiconductor integrated circuit device has a negative voltage generation circuit provided at each power supply circuit unit for six memory macros. Therefore, the response with respect to variation in a negative voltage is increased. In a standby mode, a negative voltage supply line for the six memory macros is connected by a switch circuit, and only a negative voltage generation circuit of one power supply circuit unit among six negative voltage generation circuits of the six power supply circuit units is rendered active. Thus, increase in standby current can be prevented.
Abstract translation: 半导体集成电路器件具有设置在每个用于六个存储器宏的电源电路单元的负电压产生电路。 因此，相对于负电压的变化的响应增加。 在待机模式下，通过开关电路连接六个存储器宏的负电压供给线，并且仅在六个电源电路单元的六个负电压产生电路中仅一个电源电路单元的负电压产生电路 活性。 因此，可以防止待机电流的增加。
-
公开(公告)号：US07408818B2
公开(公告)日：2008-08-05
申请号：US11703672
申请日：2007-02-08
Applicant: Kenji Yoshinaga , Masashi Matsumura , Futoshi Igaue , Mihoko Akiyama , Fukashi Morishita
Inventor： Kenji Yoshinaga , Masashi Matsumura , Futoshi Igaue , Mihoko Akiyama , Fukashi Morishita
IPC: G11C11/34
CPC classification number: G11C29/48 , G11C29/12 , G11C29/12005
Abstract: A semiconductor device has a first operation mode and a second operation mode in which power supply with a higher voltage value than that in the first operation mode is provided. The semiconductor device includes a memory portion having memory cells for storing data and a power supply circuit portion supplying a first voltage and a second voltage to the memory portion. The memory portion writes or reads data to or from the memory cells based on the first voltage and the second voltage, and the power supply circuit portion provides a smaller voltage difference between the first voltage and the second voltage in the second operation mode as compared with the voltage difference in the first operation mode.
Abstract translation: 半导体器件具有第一操作模式和第二操作模式，其中提供具有比第一操作模式中更高的电压值的电源。 半导体器件包括具有用于存储数据的存储单元的存储器部分和向存储器部分提供第一电压和第二电压的电源电路部分。 存储器部分基于第一电压和第二电压将数据写入或从存储器单元读取数据，并且电源电路部分在第二操作模式中在第一电压和第二电压之间提供较小的电压差，与第 在第一操作模式下的电压差。
-
公开(公告)号：US08004923B2
公开(公告)日：2011-08-23
申请号：US12683838
申请日：2010-01-07
Applicant: Mihoko Akiyama , Futoshi Igaue , Kenji Yoshinaga , Masashi Matsumura , Fukashi Morishita
Inventor： Mihoko Akiyama , Futoshi Igaue , Kenji Yoshinaga , Masashi Matsumura , Fukashi Morishita
IPC: G11C5/14
Abstract: A semiconductor integrated circuit device has a negative voltage generation circuit provided at each power supply circuit unit for six memory macros. Therefore, the response with respect to variation in a negative voltage is increased. In a standby mode, a negative voltage supply line for the six memory macros is connected by a switch circuit, and only a negative voltage generation circuit of one power supply circuit unit among six negative voltage generation circuits of the six power supply circuit units is rendered active. Thus, increase in standby current can be prevented.
Abstract translation: 半导体集成电路器件具有设置在每个用于六个存储器宏的电源电路单元的负电压产生电路。 因此，相对于负电压的变化的响应增加。 在待机模式下，通过开关电路连接六个存储器宏的负电压供给线，并且仅在六个电源电路单元的六个负电压产生电路中仅一个电源电路单元的负电压产生电路 活性。 因此，可以防止待机电流的增加。
-
公开(公告)号：US20100109761A1
公开(公告)日：2010-05-06
申请号：US12683838
申请日：2010-01-07
Applicant: Mihoko Akiyama , Futoshi Igaue , Kenji Yoshinaga , Masashi Matsumura , Fukashi Morishita
Inventor： Mihoko Akiyama , Futoshi Igaue , Kenji Yoshinaga , Masashi Matsumura , Fukashi Morishita
IPC: G05F1/10
Abstract: A semiconductor integrated circuit device has a negative voltage generation circuit provided at each power supply circuit unit for six memory macros. Therefore, the response with respect to variation in a negative voltage is increased. In a standby mode, a negative voltage supply line for the six memory macros is connected by a switch circuit, and only a negative voltage generation circuit of one power supply circuit unit among six negative voltage generation circuits of the six power supply circuit units is rendered active. Thus, increase in standby current can be prevented.
Abstract translation: 半导体集成电路器件具有设置在每个用于六个存储器宏的电源电路单元的负电压产生电路。 因此，相对于负电压的变化的响应增加。 在待机模式下，通过开关电路连接六个存储器宏的负电压供给线，并且仅在六个电源电路单元的六个负电压产生电路中仅一个电源电路单元的负电压产生电路 活性。 因此，可以防止待机电流的增加。
-
公开(公告)号：US20070216467A1
公开(公告)日：2007-09-20
申请号：US11717717
申请日：2007-03-14
Applicant: Mihoko Akiyama , Futoshi Igaue , Kenji Yoshinaga , Masashi Matsumura , Fukashi Morishita
Inventor： Mihoko Akiyama , Futoshi Igaue , Kenji Yoshinaga , Masashi Matsumura , Fukashi Morishita
Abstract: A semiconductor integrated circuit device has a negative voltage generation circuit provided at each power supply circuit unit for six memory macros. Therefore, the response with respect to variation in a negative voltage is increased. In a standby mode, a negative voltage supply line for the six memory macros is connected by a switch circuit, and only a negative voltage generation circuit of one power supply circuit unit among six negative voltage generation circuits of the six power supply circuit units is rendered active. Thus, increase in standby current can be prevented.
Abstract translation: 半导体集成电路器件具有设置在每个用于六个存储器宏的电源电路单元的负电压产生电路。 因此，相对于负电压的变化的响应增加。 在待机模式下，通过开关电路连接六个存储器宏的负电压供给线，并且仅在六个电源电路单元的六个负电压产生电路中仅一个电源电路单元的负电压产生电路 活性。 因此，可以防止待机电流的增加。
-
Patent Agency Ranking
公开(公告)号：US20070183214A1
公开(公告)日：2007-08-09
申请号：US11703672
申请日：2007-02-08
Applicant: Kenji Yoshinaga , Masashi Matsumura , Futoshi Igaue , Mihoko Akiyama , Fukashi Morishita
Inventor： Kenji Yoshinaga , Masashi Matsumura , Futoshi Igaue , Mihoko Akiyama , Fukashi Morishita
CPC classification number: G11C29/48 , G11C29/12 , G11C29/12005
Abstract: A semiconductor device has a first operation mode and a second operation mode in which power supply with a higher voltage value than that in the first operation mode is provided. The semiconductor device includes a memory portion having memory cells for storing data and a power supply circuit portion supplying a first voltage and a second voltage to the memory portion. The memory portion writes or reads data to or from the memory cells based on the first voltage and the second voltage, and the power supply circuit portion provides a smaller voltage difference between the first voltage and the second voltage in the second operation mode as compared with the voltage difference in the first operation mode.
Abstract translation: 半导体器件具有第一操作模式和第二操作模式，其中提供具有比第一操作模式中更高的电压值的电源。 半导体器件包括具有用于存储数据的存储单元的存储器部分和向存储器部分提供第一电压和第二电压的电源电路部分。 存储器部分基于第一电压和第二电压将数据写入或从存储器单元读取数据，并且电源电路部分在第二操作模式中在第一电压和第二电压之间提供较小的电压差，与第 在第一操作模式下的电压差。
-
公开(公告)号：US07656736B2
公开(公告)日：2010-02-02
申请号：US11717717
申请日：2007-03-14
Applicant: Mihoko Akiyama , Futoshi Igaue , Kenji Yoshinaga , Masashi Matsumura , Fukashi Morishita
Inventor： Mihoko Akiyama , Futoshi Igaue , Kenji Yoshinaga , Masashi Matsumura , Fukashi Morishita
IPC: G11C5/14
Abstract: A semiconductor integrated circuit device has a negative voltage generation circuit provided at each power supply circuit unit for six memory macros. Therefore, the response with respect to variation in a negative voltage is increased. In a standby mode, a negative voltage supply line for the six memory macros is connected by a switch circuit, and only a negative voltage generation circuit of one power supply circuit unit among six negative voltage generation circuits of the six power supply circuit units is rendered active. Thus, increase in standby current can be prevented.
Abstract translation: 半导体集成电路器件具有设置在每个用于六个存储器宏的电源电路单元的负电压产生电路。 因此，相对于负电压的变化的响应增加。 在待机模式下，通过开关电路连接六个存储器宏的负电压供给线，并且仅在六个电源电路单元的六个负电压产生电路中仅一个电源电路单元的负电压产生电路 活性。 因此，可以防止待机电流的增加。
-
公开(公告)号：US08451678B2
公开(公告)日：2013-05-28
申请号：US13080114
申请日：2011-04-05
Applicant: Mihoko Akiyama , Futoshi Igaue , Kenji Yoshinaga , Masashi Matsumura , Fukashi Morishita
Inventor： Mihoko Akiyama , Futoshi Igaue , Kenji Yoshinaga , Masashi Matsumura , Fukashi Morishita
IPC: G11C5/14
Abstract: A semiconductor integrated circuit device has a negative voltage generation circuit provided at each power supply circuit unit for six memory macros. Therefore, the response with respect to variation in a negative voltage is increased. In a standby mode, a negative voltage supply line for the six memory macros is connected by a switch circuit, and only a negative voltage generation circuit of one power supply circuit unit among six negative voltage generation circuits of the six power supply circuit units is rendered active. Thus, increase in standby current can be prevented.
Abstract translation: 半导体集成电路器件具有设置在每个用于六个存储器宏的电源电路单元的负电压产生电路。 因此，相对于负电压的变化的响应增加。 在待机模式下，通过开关电路连接六个存储器宏的负电压供给线，并且仅在六个电源电路单元的六个负电压产生电路中仅一个电源电路单元的负电压产生电路 活性。 因此，可以防止待机电流的增加。
-
公开(公告)号：US20080298156A1
公开(公告)日：2008-12-04
申请号：US12170055
申请日：2008-07-09
Applicant: Kenji YOSHINAGA , Masashi Matsumura , Futoshi Igaue , Mihoko Akiyama , Fukashi Morishita
Inventor： Kenji YOSHINAGA , Masashi Matsumura , Futoshi Igaue , Mihoko Akiyama , Fukashi Morishita
IPC: G11C5/14
CPC classification number: G11C29/48 , G11C29/12 , G11C29/12005
Abstract: A semiconductor device has a first operation mode and a second operation mode in which power supply with a higher voltage value than that in the first operation mode is provided. The semiconductor device includes a memory portion having memory cells for storing data and a power supply circuit portion supplying a first voltage and a second voltage to the memory portion. The memory portion writes or reads data to or from the memory cells based on the first voltage and the second voltage, and the power supply circuit portion provides a smaller voltage difference between the first voltage and the second voltage in the second operation mode as compared with the voltage difference in the first operation mode.
Abstract translation: 半导体器件具有第一操作模式和第二操作模式，其中提供具有比第一操作模式中更高的电压值的电源。 半导体器件包括具有用于存储数据的存储单元的存储器部分和向存储器部分提供第一电压和第二电压的电源电路部分。 存储器部分基于第一电压和第二电压将数据写入或从存储器单元读取数据，并且电源电路部分在第二操作模式中在第一电压和第二电压之间提供较小的电压差，与第 在第一操作模式下的电压差。
-
10.发明授权Semiconductor device with a well wherein a scaling down of the layout is achieved 失效具有井的半导体器件，其中实现了布局的缩小公开(公告)号：US06472716B2
公开(公告)日：2002-10-29
申请号：US09961190
申请日：2001-09-24
Applicant: Futoshi Igaue , Katsumi Dosaka
Inventor： Futoshi Igaue , Katsumi Dosaka
IPC: H01L2976
CPC classification number: H01L27/10894 , H01L21/823892 , H01L27/0207 , H01L27/0928 , H01L27/10897
Abstract: A shallow P well and a deep P well are formed in the surface of a P type semiconductor substrate so as to partially overlap each other and these wells are surrounded by an N well, a deep bottom N type well and a connection N well. The impurity concentration of this overlapping region is higher than the impurity concentration of the P well or of the deep P well and a P+ type region is formed in the surface of the overlapping region. A potential (VBB) different from the ground potential is applied to the P+ type region. The P+ type region is formed in overlapping region and, thereby, the layout of the semiconductor device can be scaled down.
Abstract translation: 在P型半导体衬底的表面中形成浅P阱和深P阱，以便部分地彼此重叠，并且这些阱被N阱，深底N型阱和连接N阱包围。 该重叠区域的杂质浓度高于P阱或深P阱的杂质浓度，并且在重叠区域的表面形成P +型区域。 不同于地电位的电位（VBB）被施加到P +型区域。 P +型区域形成在重叠区域，从而可以缩小半导体器件的布局。
-
-
-
-
-
-
-
-
-
Search Results
10
records
(took 0.014 seconds)
