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公开(公告)号：US20130113043A1
公开(公告)日：2013-05-09
申请号：US13292629
申请日：2011-11-09
IPC分类号： H01L27/12 , G06F17/50 , H01L21/336
CPC分类号： H01L21/84 , H01L27/1108 , H01L27/1203
摘要： A radiation hardened static memory cell, methods of manufacture and design structures are provided. The method includes forming one or more first gate stacks and second gate stacks on a substrate. The method further includes providing a shallow implant process for the one or more first gate stacks such that diffusion regions of the one or more first gate stacks are non-butted junction regions. The method further includes providing a deep implant process for the one or more second gates stack such that diffusions regions of the one or more second gate stacks are butted junction regions.
摘要翻译： 提供了辐射硬化的静电记忆单元，制造方法和设计结构。 该方法包括在衬底上形成一个或多个第一栅极叠层和第二栅极叠层。 该方法还包括为一个或多个第一栅极堆叠提供浅注入工艺，使得一个或多个第一栅极叠层的扩散区域是非对接结的区域。 所述方法还包括为所述一个或多个第二栅极堆叠提供深度注入工艺，使得所述一个或多个第二栅极叠层的扩散区域为对接结区域。
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2.发明授权Measurement methodology and array structure for statistical stress and test of reliabilty structures 失效统计应力的测量方法和阵列结构以及可靠性结构的测试公开(公告)号：US08120356B2
公开(公告)日：2012-02-21
申请号：US12482999
申请日：2009-06-11
IPC分类号： G01V3/00
CPC分类号： G01R31/2621 , G01R31/318511
摘要： System and method for obtaining statistics in a fast and simplified manner at the wafer level while using wafer-level test equipment. The system and method performs a parallel stress of all of the DUTs on a given chip to keep the stress time short, and then allows each DUT on that chip to be tested individually while keeping the other DUTs on that chip under stress to avoid any relaxation. In one application, the obtained statistics enable analysis of Negative Temperature Bias Instability (NTBI) phenomena of transistor devices. Although obtaining statistics may be more crucial for NBTI because of its known behavior as the device narrows, the structure and methodology, with minor appropriate adjustments, could be used for stressing multiple DUTs for many technology reliability mechanisms.
摘要翻译： 在使用晶片级测试设备的同时，在晶片级以快速和简化的方式获得统计数据的系统和方法。 该系统和方法在给定芯片上执行所有DUT的并联应力，以保持应力时间短，然后允许对该芯片上的每个DUT进行单独测试，同时将该芯片上的其他DUT保持在应力状态，以避免任何松弛 。 在一个应用中，获得的统计数据使得能够分析晶体管器件的负温度偏置不稳定性（NTBI）现象。 虽然获得统计数据可能对于NBTI而言更为重要，因为器件缩小时其已知的行为，结构和方法以及较小的适当调整可用于强调多个DUT用于许多技术可靠性机制。
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3.发明申请MEASUREMENT METHODOLOGY AND ARRAY STRUCTURE FOR STATISTICAL STRESS AND TEST OF RELIABILTY STRUCTURES 失效统计应力的测量方法和阵列结构和可靠性结构测试公开(公告)号：US20100318313A1
公开(公告)日：2010-12-16
申请号：US12482999
申请日：2009-06-11
CPC分类号： G01R31/2621 , G01R31/318511
摘要： System and method for obtaining statistics in a fast and simplified manner at the wafer level while using wafer-level test equipment. The system and method performs a parallel stress of all of the DUTs on a given chip to keep the stress time short, and then allows each DUT on that chip to be tested individually while keeping the other DUTs on that chip under stress to avoid any relaxation. In one application, the obtained statistics enable analysis of Negative Temperature Bias Instability (NTBI) phenomena of transistor devices. Although obtaining statistics may be more crucial for NBTI because of its known behavior as the device narrows, the structure and methodology, with minor appropriate adjustments, could be used for stressing multiple DUTs for many technology reliability mechanisms.
摘要翻译： 在使用晶片级测试设备的同时，在晶片级以快速和简化的方式获得统计数据的系统和方法。 该系统和方法在给定芯片上执行所有DUT的并联应力，以保持应力时间短，然后允许对该芯片上的每个DUT进行单独测试，同时将该芯片上的其他DUT保持在应力状态，以避免任何松弛 。 在一个应用中，获得的统计数据使得能够分析晶体管器件的负温度偏置不稳定性（NTBI）现象。 虽然获得统计数据可能对于NBTI而言更为重要，因为器件缩小时其已知的行为，结构和方法以及较小的适当调整可用于强调多个DUT用于许多技术可靠性机制。
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公开(公告)号：US09006827B2
公开(公告)日：2015-04-14
申请号：US13292629
申请日：2011-11-09
CPC分类号： H01L21/84 , H01L27/1108 , H01L27/1203
摘要： A radiation hardened static memory cell, methods of manufacture and design structures are provided. The method includes forming one or more first gate stacks and second gate stacks on a substrate. The method further includes providing a shallow implant process for the one or more first gate stacks such that diffusion regions of the one or more first gate stacks are non-butted junction regions. The method further includes providing a deep implant process for the one or more second gates stack such that diffusions regions of the one or more second gate stacks are butted junction regions.
摘要翻译： 提供了辐射硬化的静电记忆单元，制造方法和设计结构。 该方法包括在衬底上形成一个或多个第一栅极叠层和第二栅极叠层。 该方法还包括为一个或多个第一栅极堆叠提供浅注入工艺，使得一个或多个第一栅极叠层的扩散区域是非对接结的区域。 所述方法还包括为所述一个或多个第二栅极堆叠提供深度注入工艺，使得所述一个或多个第二栅极叠层的扩散区域为对接结区域。
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