公开(公告)号：US5227999A

公开(公告)日：1993-07-13

申请号：US681747

申请日：1991-04-08

申请人： Makoto Ihara ,  Kazuaki Ochiai

发明人： Makoto Ihara ,  Kazuaki Ochiai

IPC分类号： G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  H01L21/82 ,  H01L27/10

CPC分类号： G11C29/781

摘要： A semiconductor memory device has a plurality of pairs of bit lines and one or more pairs of redundant bit lines to replace faulty bit lines, if any. The redundant bit lines are connected with a first pair of data lines, which is connected to a differential amplifier, by respective second switches, and the bit lines are connected with a second pair of data lines by respective first switches. A third switch is provided between the first and second data lines, and the second data lines are connected to or disconnected from the first data lines by the third switch. There are also provided column decoders connected to the respective first switches and redundant column decoders connected to both the respective second switches and the third switch. When either redundant column decoder outputs a redundant signal for connecting the redundant bit lines to the first data lines, the third switch is turned off to disconnect the second data lines from the first data lines and therefore from the differential amplifier. On the other hand, when every redundant column decoder outputs a non-redundant signal for disconnecting the redundant bit lines from the first data lines, the third switch is turned on to connect the second data lines to the first data lines and therefore to the differential amplifier.

摘要翻译： 半导体存储器件具有多对位线和一对或多对冗余位线来代替有缺陷的位线（如果有的话）。 冗余位线与通过相应的第二开关连接到差分放大器的第一对数据线连接，并且位线通过相应的第一开关与第二对数据线连接。 第三开关设置在第一和第二数据线之间，第二数据线通过第三开关与第一数据线连接或断开。 还提供了连接到相应的第一开关和连接到相应的第二开关和第三开关的冗余列解码器的列解码器。 当冗余列解码器输出用于将冗余位线连接到第一数据线的冗余信号时，第三开关被断开以将第二数据线与第一数据线断开，因此从差分放大器断开。 另一方面，当每个冗余列解码器输出用于从第一数据线断开冗余位线的非冗余信号时，第三开关导通以将第二数据线连接到第一数据线并因此连接到差分 放大器

公开(公告)号：US06866811B2

公开(公告)日：2005-03-15

申请号：US09842255

申请日：2001-04-26

申请人： Yoshihiro Kayano ,  Hiroyuki Imaizumi ,  Kazuaki Ochiai

发明人： Yoshihiro Kayano ,  Hiroyuki Imaizumi ,  Kazuaki Ochiai

IPC分类号： B29C45/26 ,  B29C45/00 ,  B29C45/13 ,  B29C45/16 ,  B29C45/17 ,  B29L9/00 ,  B29L22/00

CPC分类号： B29C45/1704 ,  B29C45/1639 ,  B29C45/1705

摘要： An injection-molding apparatus comprises a mold assembly having a first-molten-resin injection portion for injecting a first molten thermoplastic resin into a cavity of the mold assembly, a second-molten-resin injection portion for injecting a second molten thermoplastic resin into the cavity, and a pressurized-fluid introducing portion for introducing a pressurized fluid into the second molten thermoplastic resin injected into the cavity. The injection-molding apparatus also comprises a first injection cylinder communicating with the first-molten-resin injection portion, and a second injection cylinder communicating with the second-molten-resin injection portion.

摘要翻译： 注射成型装置包括：模具组件，其具有用于将第一熔融热塑性树脂注射到模具组件的空腔中的第一熔融树脂注入部分，用于将第二熔融热塑性树脂注入到模具组件中的第二熔融树脂注射部分 空腔和用于将加压流体引入注入到空腔中的第二熔融热塑性树脂中的加压流体引入部分。 注射成型装置还包括与第一熔融树脂注射部分连通的第一注射圆筒和与第二熔融树脂注射部分连通的第二注射圆筒。

公开(公告)号：US5185722A

公开(公告)日：1993-02-09

申请号：US616923

申请日：1990-11-21

申请人： Yoshiji Ota ,  Kazuaki Ochiai

发明人： Yoshiji Ota ,  Kazuaki Ochiai

IPC分类号： G11C29/24 ,  G11C29/38

CPC分类号： G11C29/24 ,  G11C29/38

摘要： A semiconductor memory device has an array of examined memory cells, and reference memory cells in a column. The examined memory cells in each column and the reference memory cells are connected with respective pairs of complementary bit lines connected with sense amplifiers. Each reference memory cell and the examined memory cells in each row are connected with corresponding word lines. The device also has a line data memory circuit, a bit line select circuit and a plurality of output evaluation circuits connected with the bit line pairs for the examined memory cells. In a test mode, identical data is simultaneously written to the reference and examined memory cells connected with each word line. The line data memory circuit outputs data from the reference memory cell as expected data, in response to which, the bit line select circuit selects one of the bit lines for each of the examined memory cells when the expected data is LOW, and the other of the bit lines when the expected data is HIGH. Each output evaluation circuit simultaneously detects an output from a corresponding examined memory cell via the one bit line or the other bit line selected in accordance with the expected data, and outputs a signal indicating coincidence or non-coincidence between the output signal detected and the expected value. Thus the device tests its own operation through a parallel access to the memory cells.

摘要翻译： 半导体存储器件具有检查的存储器单元阵列和列中的参考存储器单元。 每列中检查的存储单元和参考存储单元与与读出放大器连接的各对互补位线连接。 每个参考存储单元和每行中检查的存储单元与对应的字线连接。 该装置还具有线数据存储电路，位线选择电路和与被检查存储单元的位线对连接的多个输出评估电路。 在测试模式中，相同的数据被同时写入与每个字线连接的参考和检查的存储器单元。 线数据存储器电路将来自参考存储单元的数据作为期望数据输出，响应于此，位线选择电路在预期数据为低电平时选择每个被检查的存储器单元的位线之一，另一个 当预期数据为高电平时的位线。 每个输出评估电路经由根据预期数据选择的一个位线或另一个位线同时检测来自对应的已检查存储单元的输出，并输出指示检测到的输出信号与预期的一致或不一致的信号 值。 因此，器件通过并行访问存储器单元来测试其自身的操作。

公开(公告)号：US5202888A

公开(公告)日：1993-04-13

申请号：US500601

申请日：1990-03-28

申请人： Kazuaki Ochiai

发明人： Kazuaki Ochiai

IPC分类号： G06F12/16 ,  G11C29/00 ,  G11C29/12 ,  G11C29/34

CPC分类号： G11C29/34

摘要： A semiconductor memory device has a multibit parallel test function and a method of testing such a memory device. The memory device comprises a multibit parallel writing circuit (2) and a multibit parallel check circuit (3). The method comprises the steps of: inputting test data into a memory unit through an input (4) while setting the multibit parallel writing circuit (2) to the ON state by a control circuit; reading out the multibit test data from the memory unit, while setting the multibit parallel check circuit (3) to the OFF state, thereby conducting the test of the multibit parallel writing circuit (2) inputting multibit test data into the memory unit through the input, while setting the multibit parallel writing circuit (2) to the OFF state by the control circuit; and reading out the multibit test data from the memory unit, while setting the multibit parallel check circuit (3) to the ON state, thereby conducting the test of said multibit parallel check circuit (3).

摘要翻译： 半导体存储器件具有多位并行测试功能和测试这种存储器件的方法。 存储器件包括多位并行写入电路（2）和多位并行校验电路（3）。 该方法包括以下步骤：通过控制电路将多位并行写入电路（2）设置为ON状态，通过输入（4）将测试数据输入到存储器单元中; 在将多位并行检查电路（3）设置为OFF状态的同时，从存储器单元读出多位测试数据，从而进行多位并行写入电路（2）的测试，通过输入将多位测试数据输入存储器单元 同时通过控制电路将多位并行写入电路（2）设置为OFF状态; 以及在将多位并行检查电路（3）设置为ON状态的同时，从存储器单元读出多位测试数据，从而进行所述多位并行检查电路（3）的测试。