公开(公告)号：US08710548B2

公开(公告)日：2014-04-29

申请号：US12795143

申请日：2010-06-07

申请人： Manabu Yanagihara ,  Kazushi Nakazawa ,  Tsuyoshi Tanaka

发明人： Manabu Yanagihara ,  Kazushi Nakazawa ,  Tsuyoshi Tanaka

IPC分类号： H01L29/778

CPC分类号： H01L29/66462 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/402 ,  H01L29/7787 ,  H01L29/872

摘要： A semiconductor device includes a first semiconductor layer which is formed above a substrate, a Schottky electrode and an ohmic electrode which are formed on the first semiconductor layer to be spaced from each other and a second semiconductor layer which is formed to cover the first semiconductor layer with the Schottky electrode and the ohmic electrode exposed. The second semiconductor layer has a larger band gap than that of the first semiconductor layer.

摘要翻译： 半导体器件包括形成在衬底上的第一半导体层，形成在第一半导体层上彼此间隔开的肖特基电极和欧姆电极以及形成为覆盖第一半导体层的第二半导体层 肖特基电极和欧姆电极暴露。 第二半导体层具有比第一半导体层更大的带隙。

公开(公告)号：US08526207B2

公开(公告)日：2013-09-03

申请号：US13158934

申请日：2011-06-13

申请人： Hiroto Yamagiwa ,  Shingo Hashizume ,  Manabu Yanagihara ,  Ayanori Ikoshi

发明人： Hiroto Yamagiwa ,  Shingo Hashizume ,  Manabu Yanagihara ,  Ayanori Ikoshi

IPC分类号： H02M7/02 ,  H03K17/94 ,  H03K17/687

CPC分类号： H01L29/7787 ,  H01L29/2003 ,  H01L29/42316 ,  H03K17/6871 ,  H03K2017/6875 ,  H03K2217/0009

摘要： A semiconductor device 101 in a bi-directional switch includes: a first electrode 109A, a second electrode 109B, a first gate electrode 112A, and a second gate electrode 112B. In a transition period: when the potential of the first electrode 109A is higher than the potential of the second electrode 109B, a voltage lower than the first threshold voltage is applied to the first gate electrode 112A and a voltage higher than the second threshold value voltage is applied to the second gate electrode 112B; and otherwise, a voltage higher than the first threshold value voltage is applied to the first gate electrode, and a voltage lower than the second threshold value voltage is applied to the second gate electrode.

摘要翻译： 双向开关中的半导体器件101包括：第一电极109A，第二电极109B，第一栅电极112A和第二栅电极112B。 在过渡期间：当第一电极109A的电位高于第二电极109B的电位时，将低于第一阈值电压的电压施加到第一栅电极112A，并且施加高于第二阈值电压 施加到第二栅电极112B; 否则，将高于第一阈值电压的电压施加到第一栅电极，并且将低于第二阈值电压的电压施加到第二栅电极。

公开(公告)号：US08405126B2

公开(公告)日：2013-03-26

申请号：US13196512

申请日：2011-08-02

申请人： Daisuke Shibata ,  Tatsuo Morita ,  Manabu Yanagihara ,  Yasuhiro Uemoto

发明人： Daisuke Shibata ,  Tatsuo Morita ,  Manabu Yanagihara ,  Yasuhiro Uemoto

IPC分类号： H01L29/778

CPC分类号： H01L29/7783 ,  H01L27/0605 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/7787

摘要： A semiconductor device includes a semiconductor layer stack formed on a substrate, a first ohmic electrode and a second ohmic electrode which are formed on the semiconductor layer stack, and are spaced from each other, a first control layer formed between the first ohmic electrode and the second ohmic electrode, and a first gate electrode formed on the first control layer. The first control layer includes a lower layer, an intermediate layer which is formed on the lower layer, and has lower impurity concentration than the lower layer, and an upper layer which is formed on the intermediate layer, and has higher impurity concentration than the intermediate layer.

摘要翻译： 半导体器件包括形成在衬底上的半导体层堆叠，形成在半导体层堆叠上的第一欧姆电极和第二欧姆电极，并且彼此间隔开，形成在第一欧姆电极和第二欧姆电极之间的第一控制层 第二欧姆电极和形成在第一控制层上的第一栅电极。 第一控制层包括下层，形成在下层上的中间层，并且具有比下层更低的杂质浓度，以及形成在中间层上的上层，并且具有比中间层更高的杂质浓度 层。

公开(公告)号：US08203376B2

公开(公告)日：2012-06-19

申请号：US12445390

申请日：2007-11-20

申请人： Tatsuo Morita ,  Manabu Yanagihara ,  Hidetoshi Ishida ,  Yasuhiro Uemoto ,  Hiroaki Ueno ,  Tsuyoshi Tanaka ,  Daisuke Ueda

发明人： Tatsuo Morita ,  Manabu Yanagihara ,  Hidetoshi Ishida ,  Yasuhiro Uemoto ,  Hiroaki Ueno ,  Tsuyoshi Tanaka ,  Daisuke Ueda

IPC分类号： H03K17/687

CPC分类号： H01L29/7787 ,  H01L27/0605 ,  H01L29/0619 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/432 ,  H01L29/739 ,  H01L29/8124

摘要： A semiconductor device includes a semiconductor layer stack 13 formed on a substrate 11 and having a channel region, a first electrode 16A and a second electrode 16B formed spaced apart from each other on the semiconductor layer stack 13, a first gate electrode 18A formed between the first electrode 16A and the second electrode 16B, and a second gate electrode 18B formed between the first gate electrode 18A and the second electrode 16B. A first control layer 19A having a p-type conductivity is formed between the semiconductor layer stack 13 and the first gate electrode 18A.

摘要翻译： 半导体器件包括形成在衬底11上并具有沟道区的半导体层堆叠13，在半导体层叠层13上彼此隔开形成的第一电极16A和第二电极16B，形成在第一栅电极18A之间的第一栅电极18A 第一电极16A和第二电极16B，以及形成在第一栅电极18A和第二电极16B之间的第二栅电极18B。 在半导体层堆叠13和第一栅电极18A之间形成具有p型导电性的第一控制层19A。

公开(公告)号：US08164115B2

公开(公告)日：2012-04-24

申请号：US13010238

申请日：2011-01-20

申请人： Masahiro Hikita ,  Tetsuzo Ueda ,  Manabu Yanagihara ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka

发明人： Masahiro Hikita ,  Tetsuzo Ueda ,  Manabu Yanagihara ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka

IPC分类号： H01L21/337 ,  H01L21/335

CPC分类号： H01L29/7786 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/432 ,  H01L29/66462

摘要： A nitride semiconductor device includes: a substrate; a first nitride semiconductor layer formed over the substrate; a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a larger band gap energy than the first nitride semiconductor layer; a third nitride semiconductor layer formed on the second nitride semiconductor layer and including a p-type nitride semiconductor with at least a single-layer structure; a gate electrode formed on the third nitride semiconductor layer; and a source electrode and a drain electrode formed in regions located on both sides of the gate electrode, respectively. The third nitride semiconductor layer has a thickness greater in a portion below the gate electrode than in a portion below the side of the gate electrode.

摘要翻译： 氮化物半导体器件包括：衬底; 形成在所述基板上的第一氮化物半导体层; 形成在所述第一氮化物半导体层上并且具有比所述第一氮化物半导体层更大的带隙能量的第二氮化物半导体层; 形成在所述第二氮化物半导体层上并且包括具有至少单层结构的p型氮化物半导体的第三氮化物半导体层; 形成在所述第三氮化物半导体层上的栅电极; 以及分别形成在位于栅电极两侧的区域中的源电极和漏电极。 所述第三氮化物半导体层的厚度比所述栅极电极侧的部分的厚度大。

公开(公告)号：US08148752B2

公开(公告)日：2012-04-03

申请号：US13021118

申请日：2011-02-04

申请人： Ayanori Ikoshi ,  Shingo Hashizume ,  Masahiro Hikita ,  Hiroto Yamagiwa ,  Manabu Yanagihara

发明人： Ayanori Ikoshi ,  Shingo Hashizume ,  Masahiro Hikita ,  Hiroto Yamagiwa ,  Manabu Yanagihara

IPC分类号： H01L29/778

CPC分类号： H01L29/7786 ,  H01L29/2003 ,  H01L29/41758

摘要： A field effect transistor includes a semiconductor stack formed on a substrate, and having a first nitride semiconductor layer and a second nitride semiconductor layer. A source electrode and a drain electrode are formed on the semiconductor stack so as to be separated from each other. A gate electrode is formed between the source electrode and the drain electrode so as to be separated from the source electrode and the drain electrode. A hole injection portion is formed near the drain electrode. The hole injection portion has a p-type third nitride semiconductor layer, and a hole injection electrode formed on the third nitride semiconductor layer. The hole injection electrode and the drain electrode have substantially the same potential.

摘要翻译： 场效应晶体管包括形成在衬底上的半导体堆叠，并且具有第一氮化物半导体层和第二氮化物半导体层。 源电极和漏电极形成在半导体堆叠上以便彼此分离。 在源电极和漏电极之间形成栅电极，以与源电极和漏电极分离。 在漏电极附近形成空穴注入部。 空穴注入部分具有p型第三氮化物半导体层和形成在第三氮化物半导体层上的空穴注入电极。 空穴注入电极和漏电极具有大致相同的电位。

公开(公告)号：US08076698B2

公开(公告)日：2011-12-13

申请号：US11995040

申请日：2006-06-27

申请人： Daisuke Ueda ,  Tsuyoshi Tanaka ,  Yasuhiro Uemoto ,  Tetsuzo Ueda ,  Manabu Yanagihara ,  Masahiro Hikita ,  Hiroaki Ueno

发明人： Daisuke Ueda ,  Tsuyoshi Tanaka ,  Yasuhiro Uemoto ,  Tetsuzo Ueda ,  Manabu Yanagihara ,  Masahiro Hikita ,  Hiroaki Ueno

IPC分类号： H01L31/0328

CPC分类号： H01L29/739 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/7786

摘要： In a transistor, an AlN buffer layer 102, an undoped GaN layer 103, an undoped AlGaN layer 104, a p-type control layer 105, and a p-type contact layer 106 are formed in this order on a sapphire substrate 101. The transistor further includes a gate electrode 110 in ohmic contact with the p-type contact layer 106, and a source electrode 108 and a drain electrode 109 provided on the undoped AlGaN layer 104. By applying a positive voltage to the p-type control layer 105, holes are injected into a channel to increase a current flowing in the channel.

摘要翻译： 在晶体管中，在蓝宝石衬底101上依次形成AlN缓冲层102，未掺杂的GaN层103，未掺杂的AlGaN层104，p型控制层105和p型接触层106。 晶体管还包括与p型接触层106欧姆接触的栅电极110以及设置在未掺杂的AlGaN层104上的源电极108和漏极109.通过向p型控制层105施加正电压 ，孔被注入到通道中以增加在通道中流动的电流。

公开(公告)号：US20110284928A1

公开(公告)日：2011-11-24

申请号：US13196512

申请日：2011-08-02

申请人： Daisuke SHIBATA ,  Tatsuo Morita ,  Manabu Yanagihara ,  Yasuhiro Uemoto

发明人： Daisuke SHIBATA ,  Tatsuo Morita ,  Manabu Yanagihara ,  Yasuhiro Uemoto

IPC分类号： H01L29/778 ,  H01L27/06

CPC分类号： H01L29/7783 ,  H01L27/0605 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/7787

摘要： A semiconductor device includes a semiconductor layer stack formed on a substrate, a first ohmic electrode and a second ohmic electrode which are formed on the semiconductor layer stack, and are spaced from each other, a first control layer formed between the first ohmic electrode and the second ohmic electrode, and a first gate electrode formed on the first control layer. The first control layer includes a lower layer, an intermediate layer which is formed on the lower layer, and has lower impurity concentration than the lower layer, and an upper layer which is formed on the intermediate layer, and has higher impurity concentration than the intermediate layer.

摘要翻译： 半导体器件包括形成在衬底上的半导体层堆叠，形成在半导体层堆叠上的第一欧姆电极和第二欧姆电极，并且彼此间隔开，形成在第一欧姆电极和第二欧姆电极之间的第一控制层 第二欧姆电极和形成在第一控制层上的第一栅电极。 第一控制层包括下层，形成在下层上的中间层，并且具有比下层更低的杂质浓度，以及形成在中间层上的上层，并且具有比中间层更高的杂质浓度 层。

公开(公告)号：US20110193171A1

公开(公告)日：2011-08-11

申请号：US12905801

申请日：2010-10-15

申请人： Hiroto Yamagiwa ,  Shingo Hashizume ,  Ayanori Ikoshi ,  Manabu Yanagihara ,  Yasuhiro Uemoto

发明人： Hiroto Yamagiwa ,  Shingo Hashizume ,  Ayanori Ikoshi ,  Manabu Yanagihara ,  Yasuhiro Uemoto

IPC分类号： H01L27/088

CPC分类号： H01L29/7786 ,  H01L27/0266 ,  H01L27/0605 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/41758 ,  H01L29/42364 ,  H01L29/8124 ,  H01L29/861

摘要： A semiconductor device includes a first transistor formed on a first element region, and a first protecting element including a second transistor formed on a second element region. A second protecting element ohmic electrode is connected to a first gate electrode, a first protecting element ohmic electrode is connected to a first ohmic electrode, and a first protecting element gate electrode is connected to at least one of the first protecting element ohmic electrode and the second protecting element ohmic electrode. The second element region is smaller in area than the first element region.

摘要翻译： 半导体器件包括形成在第一元件区上的第一晶体管和包括形成在第二元件区上的第二晶体管的第一保护元件。 第二保护元件欧姆电极连接到第一栅电极，第一保护元件欧姆电极连接到第一欧姆电极，第一保护元件栅电极连接至第一保护元件欧姆电极和 第二保护元件欧姆电极。 第二元件区域的面积小于第一元件区域。

公开(公告)号：US20110114967A1

公开(公告)日：2011-05-19

申请号：US13010238

申请日：2011-01-20

申请人： Masahiro HIKITA ,  Tetsuzo UEDA ,  Manabu YANAGIHARA ,  Yasuhiro UEMOTO ,  Tsuyoshi TANAKA

发明人： Masahiro HIKITA ,  Tetsuzo UEDA ,  Manabu YANAGIHARA ,  Yasuhiro UEMOTO ,  Tsuyoshi TANAKA

IPC分类号： H01L29/205 ,  H01L29/78

CPC分类号： H01L29/7786 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/432 ,  H01L29/66462

摘要： A nitride semiconductor device includes: a substrate; a first nitride semiconductor layer formed over the substrate; a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a larger band gap energy than the first nitride semiconductor layer; a third nitride semiconductor layer formed on the second nitride semiconductor layer and including a p-type nitride semiconductor with at least a single-layer structure; a gate electrode formed on the third nitride semiconductor layer; and a source electrode and a drain electrode formed in regions located on both sides of the gate electrode, respectively. The third nitride semiconductor layer has a thickness greater in a portion below the gate electrode than in a portion below the side of the gate electrode.

摘要翻译： 氮化物半导体器件包括：衬底; 形成在所述基板上的第一氮化物半导体层; 形成在所述第一氮化物半导体层上并且具有比所述第一氮化物半导体层更大的带隙能量的第二氮化物半导体层; 形成在所述第二氮化物半导体层上并且包括具有至少单层结构的p型氮化物半导体的第三氮化物半导体层; 形成在所述第三氮化物半导体层上的栅电极; 以及分别形成在位于栅电极两侧的区域中的源电极和漏电极。 所述第三氮化物半导体层的厚度比所述栅极电极侧的部分的厚度大。