公开(公告)号：US06777269B2

公开(公告)日：2004-08-17

申请号：US10411916

申请日：2003-04-11

申请人： Masahide Kakeda

发明人： Masahide Kakeda

IPC分类号： H01L2182

CPC分类号： G06F17/5045 ,  G06F17/5068 ,  H01L23/525 ,  H01L2924/0002 ,  H01L2924/00

摘要： A first signal path of a circuit 300 of the present invention is formed by connecting a restricted area 331 in the electrically disconnected state, restricted areas 321 and 311 in the electrically connected state in series, using conductors 330, 320, and 310, and contacts 351 and 352. The circuit 300 is constructed by connecting in parallel six signal paths each being divided by a combination of one or two restricted areas provided thereon. Every time the circuit state is switched, a signal path disconnected by one restricted area is changed suitably to a signal path disconnected by two restricted areas, and vice versa, so as to maintain a signal path disconnected by a combination of restricted areas. By doing so, the switch of the circuit between the disconnected state and the connected state can be repeated an unlimited number of times by a change in one freely-chosen layer.

摘要翻译： 本发明的电路300的第一信号路径是通过使用导体330,320和310将电气断开状态的限制区域331，电连接状态下的限制区域321和311串联连接而形成的， 电路300通过并联连接六个信号路径构成，每个信号路径被设置在其上的一个或两个受限区域的组合分开。 每次切换电路状态时，由一个限制区域断开的信号路径被适当地改变为由两个限制区域断开的信号路径，反之亦然，以便通过限制区域的组合来保持信号路径断开。 通过这样做，可以通过一个自由选择的层中的改变来重复断开状态和连接状态之间的电路的切换无限次。

公开(公告)号：US06564311B2

公开(公告)日：2003-05-13

申请号：US09487343

申请日：2000-01-19

申请人： Masahide Kakeda ,  Reiji Segawa

发明人： Masahide Kakeda ,  Reiji Segawa

IPC分类号： G06F1200

CPC分类号： G06F12/1036 ,  G06F12/109 ,  G06F12/1483 ,  G06F2212/656

摘要： An address translation apparatus comprises: entry storage means for storing a plurality of entries, each entry containing a virtual page number, a physical page number, and a process identifier which is composed of plural bits; comparison information storage means for storing comparison information which defines a method for comparing a process identifier possessed by a process that is currently executed, with the process identifier in each entry; process comparison means for comprising the process identifier possessed by the process that is currently executed, with the process identifier in the entry, on the basis of the comparison information; and entry retrieval means for retrieving, from the entry storage means, an entry including a virtual page number equal to a virtual page number supplied from the outside, and a process identifier which matches the process identifier of the currently executed process, according to the result of comparison by the process comparison means. Therefore, when a physical memory has a content which can be shared between at least two processes, effective utilization of memory area can be achieved by unifying entries with respect to these processes.

摘要翻译： 地址转换装置包括：条目存储装置，用于存储多个条目，每个条目包含虚拟页码，物理页号和由多个比特组成的进程标识符; 比较信息存储装置，用于存储定义用于将当前执行的处理所拥有的进程标识符与每个条目中的进程标识符进行比较的方法的比较信息; 处理比较装置，用于根据比较信息，将当前执行的进程所拥有的进程标识符与条目中的进程标识符相结合; 以及条目检索装置，用于从条目存储装置检索包括等于从外部提供的虚拟页码的虚拟页码的条目以及与当前执行的处理的处理标识符相匹配的处理标识符，根据该结果 通过过程比较手段进行比较。 因此，当物理存储器具有能够在至少两个进程之间共享的内容时，可以通过统一关于这些处理的条目来实现存储区域的有效利用。

公开(公告)号：US20090187903A1

公开(公告)日：2009-07-23

申请号：US12346987

申请日：2008-12-31

申请人： Akira UEDA ,  Takao YAMAMOTO ,  Shinji OZAKI ,  Masahide KAKEDA

发明人： Akira UEDA ,  Takao YAMAMOTO ,  Shinji OZAKI ,  Masahide KAKEDA

IPC分类号： G06F9/455

CPC分类号： G06F9/45558 ,  G06F11/3636 ,  G06F11/3648 ,  G06F2009/45591

摘要： A virtual multiprocessor system which does not require a memory apparatus for debugging includes: a physical processor, storage units for storing status information indicating respective statuses of logic processors, a dispatch unit which assigns one of the logic processors by switching the logic processors with respect to a physical processor, and an interrupt unit which suspends the processing currently executed by a current logic processor among the logic processors by issuing a debug interrupt request to the current logic processor; in the virtual multiprocessor system, the dispatch unit stores status information corresponding to the current logic processor into one of the storage units in response to the debug interrupt request issued to the current logic processor that is assigned to the physical processor.

摘要翻译： 不需要用于调试的存储器装置的虚拟多处理器系统包括：物理处理器，用于存储指示逻辑处理器的各自状态的状态信息的存储单元，调度单元，其通过将逻辑处理器相对于 物理处理器和中断单元，其通过向当前逻辑处理器发出调试中断请求来暂停当前逻辑处理器在逻辑处理器中执行的处理; 在虚拟多处理器系统中，调度单元响应于发送给分配给物理处理器的当前逻辑处理器的调试中断请求，将与当前逻辑处理器相对应的状态信息存储到一个存储单元中。

公开(公告)号：US20070088896A1

公开(公告)日：2007-04-19

申请号：US11510670

申请日：2006-08-28

申请人： Masahide Kakeda ,  Masaitsu Nakajima ,  Takao Yamamoto ,  Shinji Ozaki

发明人： Masahide Kakeda ,  Masaitsu Nakajima ,  Takao Yamamoto ,  Shinji Ozaki

IPC分类号： G06F12/08 ,  G06F13/00

CPC分类号： G06F12/0893 ,  G06F12/0831

摘要： A cache access transmission means outputs an access address, obtained from a CPU by way of a local cache access address input means, to a shared address bus via a remote cache access address output means. A cache access control means accesses a cache memory by using the access address obtained from the shared address bus by way of a remote cache access address input means. That is, an access address output from a CPU of a first processor is output from the cache access transmission means and received by the cache access control means so as to be used in accessing a cache memory in a second processor.

摘要翻译： 高速缓存存取传输装置经由远程高速缓存存取地址输出装置将通过本地高速缓存存取地址输入装置从CPU获得的访问地址输出到共享地址总线。 高速缓存访​​问控制装置通过使用通过远程高速缓存访​​问地址输入装置从共享地址总线获得的访问地址来访问高速缓冲存储器。 也就是说，从高速缓存访​​问传输装置输出从第一处理器的CPU输出的访问地址，并由高速缓存访​​问控制装置接收，以便用于访问第二处理器中的高速缓冲存储器。

公开(公告)号：US20120023311A1

公开(公告)日：2012-01-26

申请号：US13215623

申请日：2011-08-23

申请人： Takao YAMAMOTO ,  Shinji OZAKI ,  Masahide KAKEDA ,  Masaitsu NAKAJIMA

发明人： Takao YAMAMOTO ,  Shinji OZAKI ,  Masahide KAKEDA ,  Masaitsu NAKAJIMA

IPC分类号： G06F9/48 ,  G06F9/40

CPC分类号： G06F9/462 ,  G06F9/30101 ,  G06F9/30123 ,  G06F9/3851 ,  G06F9/3885

摘要： A processor apparatus according to the present invention is a processor apparatus which shares hardware resources between a plurality of processors, and includes: a first determination unit which determines whether or not a register in each of the hardware resources holds extension context data of a program that is currently executed; a second determination unit which determines to which processor the extension context data in the hardware resource corresponds; a first transfer unit which saves and restores the extension context data between programs in the processor; and a second transfer unit which saves and restores the extension context data between programs between different processors.

摘要翻译： 根据本发明的处理器装置是在多个处理器之间共享硬件资源的处理器装置，包括：第一确定单元，确定每个硬件资源中的寄存器是否保存有程序的扩展上下文数据， 目前执行; 第二确定单元，确定硬件资源中的扩展上下文数据对哪个处理器; 第一传送单元，其在所述处理器中的节目之间保存和恢复所述扩展上下文数据; 以及第二传送单元，其在不同处理器之间的节目之间保存和恢复扩展上下文数据。

公开(公告)号：US20060059317A1

公开(公告)日：2006-03-16

申请号：US11223932

申请日：2005-09-13

申请人： Masahide Kakeda

发明人： Masahide Kakeda

IPC分类号： G06F12/00

CPC分类号： G06F12/0833

摘要： The multiprocessing apparatus of the present invention is a multiprocessing apparatus including a plurality of processors, a shared bus, and a shared bus controller, wherein each of the processors includes a central processing unit (CPU) and a local cache, each of the local caches includes a cache memory, and a cache control unit that controls the cache memory, each of the cache control units includes a data coherence management unit that manages data coherence between the local caches by controlling data transfer carried out, via the shared bus, between the local caches, wherein at least one of the cache control units (a) monitors a local cache access signal, outputted from another one of the processors, for notifying an occurrence of a cache miss, and (b) notifies pseudo information to the another one of the processors via the shared bus controller, the pseudo information indicating that data corresponding to the local cache access signal is stored in the cache memory of the local cache that includes the at least one of the cache control units, even in the case where the data corresponding to the local cache access signal is not actually stored.

摘要翻译： 本发明的多处理装置是包括多个处理器，共享总线和共享总线控制器的多处理装置，其中每个处理器包括中央处理单元（CPU）和本地高速缓存，每个本地高速缓存 包括高速缓冲存储器和控制高速缓存存储器的高速缓存控制单元，每个高速缓存控制单元包括数据一致性管理单元，其通过经由共享总线控制经由共享总线执行的数据传输来管理本地高速缓存之间的数据一致性 本地高速缓存，其中至少一个高速缓存控制单元（a）监视从另一个处理器输出的本地高速缓存访​​问信号，用于通知高速缓存未命中的发生，以及（b）将伪信息通知另一个 处理器经由共享总线控制器，指示对应于本地高速缓存访​​问信号的数据的伪信息被存储在本地ca 即使在实际上不存储与本地高速缓存访​​问信号对应的数据的情况下，也包含至少一个缓存控制单元。

公开(公告)号：US06573605B2

公开(公告)日：2003-06-03

申请号：US10186760

申请日：2002-07-01

申请人： Masahide Kakeda

发明人： Masahide Kakeda

IPC分类号： H01L2312

CPC分类号： G06F17/5045 ,  G06F17/5068 ,  H01L23/525 ,  H01L2924/0002 ,  H01L2924/00

摘要： A first signal path of a circuit 300 of the present invention is formed by connecting a restricted area 331 in the electrically disconnected state, restricted areas 321 and 311 in the electrically connected state in series, using conductors 330, 320, and 310, and contacts 351 and 352. The circuit 300 is constructed by connecting in parallel six signal paths each being divided by a combination of one or two restricted areas provided thereon. Every time the circuit state is switched, a signal path disconnected by one restricted area is changed suitably to a signal path disconnected by two restricted areas, and vice versa, so as to maintain a signal path disconnected by a combination of restricted areas. By doing so, the switch of the circuit between the disconnected state and the connected state can be repeated an unlimited number of times by a change in one freely-chosen layer.

摘要翻译： 本发明的电路300的第一信号路径是通过使用导体330,320和310将电气断开状态的限制区域331，电连接状态下的限制区域321和311串联连接而形成的， 电路300通过并联连接六个信号路径构成，每个信号路径被设置在其上的一个或两个受限区域的组合分开。 每次切换电路状态时，由一个限制区域断开的信号路径适当地改变为由两个限制区域断开的信号路径，反之亦然，以便通过限制区域的组合来保持信号路径断开。 通过这样做，可以通过一个自由选择的层中的改变来重复断开状态和连接状态之间的电路的切换无限次。

公开(公告)号：US08850168B2

公开(公告)日：2014-09-30

申请号：US13215623

申请日：2011-08-23

申请人： Takao Yamamoto ,  Shinji Ozaki ,  Masahide Kakeda ,  Masaitsu Nakajima

发明人： Takao Yamamoto ,  Shinji Ozaki ,  Masahide Kakeda ,  Masaitsu Nakajima

IPC分类号： G06F9/38 ,  G06F9/46 ,  G06F9/30

CPC分类号： G06F9/462 ,  G06F9/30101 ,  G06F9/30123 ,  G06F9/3851 ,  G06F9/3885

摘要： A processor apparatus according to the present invention is a processor apparatus which shares hardware resources between a plurality of processors, and includes: a first determination unit which determines whether or not a register in each of the hardware resources holds extension context data of a program that is currently executed; a second determination unit which determines to which processor the extension context data in the hardware resource corresponds; a first transfer unit which saves and restores the extension context data between programs in the processor; and a second transfer unit which saves and restores the extension context data between programs between different processors.

摘要翻译： 根据本发明的处理器装置是在多个处理器之间共享硬件资源的处理器装置，包括：第一确定单元，确定每个硬件资源中的寄存器是否保存有程序的扩展上下文数据， 目前执行; 第二确定单元，确定硬件资源中的扩展上下文数据对哪个处理器; 第一传送单元，其在所述处理器中的节目之间保存和恢复所述扩展上下文数据; 以及第二传送单元，其在不同处理器之间的节目之间保存和恢复扩展上下文数据。

公开(公告)号：US20120008674A1

公开(公告)日：2012-01-12

申请号：US13209804

申请日：2011-08-15

申请人： Takao YAMAMOTO ,  Shinji OZAKI ,  Masahide KAKEDA ,  Masaitsu NAKAJIMA

发明人： Takao YAMAMOTO ,  Shinji OZAKI ,  Masahide KAKEDA ,  Masaitsu NAKAJIMA

IPC分类号： H04N11/02 ,  G06F12/10

CPC分类号： G06F9/52 ,  G06F12/1027

摘要： A multithread processor including: an execution unit including a physical processor; and a translation lookaside buffer (TLB) which converts, to a physical address, a logical address output from the execution unit, and logical processors are implemented on the physical processor, a first logical processor that is a part of the logical processors constitutes a first subsystem having a first virtual space, a second logical processor that is a part of the logical processors and different from the first logical processor constitutes a second subsystem having a second virtual space, each of the first and the second subsystems has processes to be assigned to the logical processors, and the logical address includes: a first TLB access virtual identifier for identifying one of the first and the second subsystems; and a process identifier for identifying a corresponding one of the processes in each of the first and the second subsystems.

摘要翻译： 一种多线程处理器，包括：包括物理处理器的执行单元; 以及翻译后备缓冲器（TLB），其将物理地址转换为从执行单元输出的逻辑地址，并且在物理处理器上实现逻辑处理器，作为逻辑处理器的一部分的第一逻辑处理器构成第一 具有第一虚拟空间的子系统，作为逻辑处理器的一部分并且不同于第一逻辑处理器的第二逻辑处理器构成具有第二虚拟空间的第二子系统，第一和第二子系统中的每一个具有被分配给 逻辑处理器和逻辑地址包括：用于识别第一和第二子系统之一的第一TLB访问虚拟标识符; 以及用于识别第一和第二子系统中的每一个中的相应一个处理的进程标识符。

公开(公告)号：US07539823B2

公开(公告)日：2009-05-26

申请号：US11223932

申请日：2005-09-13

申请人： Masahide Kakeda

发明人： Masahide Kakeda

IPC分类号： G06F13/22

CPC分类号： G06F12/0833

摘要： A multiprocessing apparatus includes a cache control unit which monitors a local cache access signal, outputted from a processor, for notifying an occurrence of a cache miss, and notifies pseudo information to the processor via a shared bus controller, the pseudo information indicating that data corresponding to the local cache access signal is stored in a cache memory of a local cache that includes the cache control unit when the data corresponding to the local cache access signal is not actually stored in the cache memory.

摘要翻译： 多处理装置包括高速缓存控制单元，其监视从处理器输出的用于通知高速缓存未命中的发生的本地高速缓存访​​问信号，并且经由共享总线控制器将伪信息通知给处理器，伪信息指示对应的数据 当本地高速缓存访​​问信号的数据实际上不存储在高速缓冲存储器中时，本地高速缓存访​​问信号被存储在包括高速缓存控制单元的本地高速缓存的高速缓冲存储器中。